Can't set frequency more than 48MHz on STM32F767ZI

I configure the RCC for 48 MHz as follows:

    rcc.cr.modify(|_, w| w.hseon().on());
    while rcc.cr.read().hserdy().is_not_ready() {}
    println!("{:b}", rcc.cr.read().bits());
    println!("Hse ready");

    rcc.pllcfgr.modify(|_, w| w.pllsrc().hse());
    rcc.pllcfgr.modify(unsafe {|_, w| w.pllm().bits(4)});
    rcc.pllcfgr.modify(unsafe {|_, w| w.plln().bits(96)});
    rcc.pllcfgr.modify(|_, w| w.pllp().div4());

    rcc.cr.modify(|_, w| w.pllon().on());
    while rcc.cr.read().pllrdy().is_not_ready() {}
    println!("Pll ready");

    rcc.cfgr.modify(|_, w| w.sw().pll());
    while !rcc.cfgr.read().sws().is_pll() {}
    println!("pll selectected");

and it is working. If I configure the RCC to 54 MHz as follows:

    rcc.cr.modify(|_, w| w.hseon().on());
    while rcc.cr.read().hserdy().is_not_ready() {}
    println!("{:b}", rcc.cr.read().bits());
    println!("Hse ready");

    rcc.pllcfgr.modify(|_, w| w.pllsrc().hse());
    rcc.pllcfgr.modify(unsafe {|_, w| w.pllm().bits(4)});
    rcc.pllcfgr.modify(unsafe {|_, w| w.plln().bits(108)});
    rcc.pllcfgr.modify(|_, w| w.pllp().div4());

    rcc.cr.modify(|_, w| w.pllon().on());
    while rcc.cr.read().pllrdy().is_not_ready() {}
    println!("Pll ready");

    rcc.cfgr.modify(|_, w| w.sw().pll());
    while !rcc.cfgr.read().sws().is_pll() {}
    println!("pll selectected");

I get this error:

ERROR probe_rs::architecture::arm::core::armv7m: The core is in locked up status as a result of an unrecoverable exception
Error: Failed to attach to RTT

Caused by:
    RTT Initialized correctly, but there were no active channels configured

I have tried setting the prescaler ABP1 to DIV2, but it doesn't help me. How can I solve this problem?

I set the FLASH_ACR register appropriately and the problem was solved:

    rcc.cr.modify(|_, w| w.hseon().on());
    while rcc.cr.read().hserdy().is_not_ready() {}
    println!("Hse ready");

    rcc.pllcfgr.modify(|_, w| w.pllsrc().hse());
    rcc.pllcfgr.modify(unsafe {|_, w| w.pllm().bits(4)});
    rcc.pllcfgr.modify(unsafe {|_, w| w.plln().bits(108)});
    rcc.pllcfgr.modify(|_, w| w.pllp().div2());

    rcc.cr.modify(|_, w| w.pllon().on());
    while rcc.cr.read().pllrdy().is_not_ready() {}
    println!("Pll ready");

    dp.FLASH.acr.modify(|_, w| w.latency().ws9());
    while !dp.FLASH.acr.read().latency().is_ws9() {}

    rcc.cfgr.modify(|_, w| w
        .ppre1().div2()
        .ppre2().div2()
    );

    rcc.cfgr.modify(|_, w| w.sw().pll());
    while !rcc.cfgr.read().sws().is_pll() {}
    println!("pll selectected");