makefile

Makefile -- use variable updated by dependency?

I'm looking to create a Makefile where there are a bunch of top-level targets, and the action to build each of them is the same but with different variable values. A simplified example:

config1: CONFIGURATION=1
config1: setvars dobuild

config2: CONFIGURATION=2
config2: setvars dobuild

setvars: OUTPUTDIRECTORY=output-$(CONFIGURATION)
setvars: FORCE

dobuild: inputfile.c
        gcc -o $(OUTPUTDIRECTORY)/output inputfile.c

FORCE:

The idea being that make config1 will build output-1/output and make config2 will build output-2/output. The actual use case has more complexity to it that makes the different configurations actually meaningful.

This syntax does not appear to actually work. But, if you can grok what I'm trying to do here, is there a way to achieve this and have multiple top-level targets share the same setup code so it doesn't need to be duplicated/maintained in two locations, where that setup code initializes variables to new values that differ based on what top-level target is being built?

ETA: I wrote up an answer on this question describing in much more detail what exactly I'm hoping to achieve and what I settled on in the end, which is based on the insight in @renaud-pacalet's answer. See below.

Solution

  • The OUTPUTDIRECTORY variable is setvars-specific but setvars does not dependent on dobuild, so OUTPUTDIRECTORY is not defined for dobuild. Solution: declare dobuild as a prerequisite of setvars:

    $ cat Makefile
config1: CONFIGURATION=1
config1: setvars dobuild

config2: CONFIGURATION=2
config2: setvars dobuild

setvars: OUTPUTDIRECTORY=output-$(CONFIGURATION)
setvars: FORCE dobuild

dobuild: inputfile.c
    gcc -o $(OUTPUTDIRECTORY)/output inputfile.c

FORCE:

$ mkdir output-{1..2}
$ echo 'int main(void) { return 0; }' > inputfile.c
$ make config1
gcc -o output-1/output inputfile.c
$ make config2
gcc -o output-2/output inputfile.c