stm32spidummy-data

SPI Protocol Procedure

hey i am using ADS1292 for my own project, and myself is confused with SPI protocol.

i found some code on the internet and i found it sends and receive at one time.

for example, i want to send 0xFF to slave device.

then it sends the data first and wait for a receive.

And when receiving data, it sends a dummy byte and then receive.

Anyone please explain why they do this?

uint8_t sEE_ReadByte(void)
{
  return (sEE_SendByte(sEE_DUMMY_BYTE));
}

uint8_t sEE_SendByte(uint8_t byte)
{
  /*!< Loop while DR register in not empty */
  while (SPI_I2S_GetFlagStatus(sEE_SPI, SPI_I2S_FLAG_TXE) == RESET);

  /*!< Send byte through the SPI peripheral */
  SPI_SendData(sEE_SPI, byte);

  /*!< Wait to receive a byte => I do not understand this point*/
  while (SPI_I2S_GetFlagStatus(sEE_SPI, SPI_I2S_FLAG_RXNE) == RESET);

  /*!< Return the byte read from the SPI bus */
  return (uint8_t)SPI_ReceiveData(sEE_SPI);
}
Solution

  • They do this because this is the nature of SPI bus and this is how bus communications is done. Look:

    Data transmission

    Every SPI clock cycle is a full duplex data transmission. The master sends a bit on the MOSI pin and the slave reads it, while the slave sends a bit on the MISO pin and the master reads it. This sequence is true even if you only need an one-directional data transfer.

    See this image (from wikipedia) enter image description here

    So every transmission involve two shift registers of fixed size (8bit for ex). One is in master device and one in slave. In every clock cycle the data are shifted around. If you continue and clock out enough pulses (as many as the size of registers), the master and slave will have exchanged register values. Now you can read the data and continue. Of course that is not all. There is also

    Daisy chain configuration

    In this configuration more than one slave device is connected to the same chain of MISO and MOSI lines. Each slave's MOSI is connected to previous slave's MISO etc.. (See image below). With this configuration the clock pulses for a full cycle is now (number of devices) * (sizo of buffers)

    enter image description here

    For more information you can see also wikipedia.

    Conclusion

    As a result of the above. In order for the master to send a byte, he is forced to also receive a byte. This byte has no value for the communication. Is a dummy byte and the master discards it. And in order to receive a byte he is forced to also transmit one. Again the master transmits a dummy byte. The same is true for the slave part of communication.

    hoo2