Does STMicro wrongly interpret the term "shadow register"?

I use the STM32 family of microcontrollers, more specifically the STM32F7 series. Currently I'm investigating the use of general-purpose timers.

About double buffered registers.

Microcontrollers sometimes make use of double-buffered registers. In this way, the software can write to and read from the register without causing troubles. The following figure explains:

              buffered register:           active register:
                 --------------             --------------
                |   REGX_BUF   | <-------> |    REGX      |
                 --------------             --------------
                      |                           |
                      |                           |
                   SOFTWARE                    HARDWARE

         The software interacts        Updates to and from the
         only with the buffered        active register take place
         register.                     at specific moments (when it
                                       is 'safe').

         synonyms:                     synonyms:
           - buffered register            - active register
           - preload register
           - shadow register (?)

There are several terms for both REGX_BUF and REGX from the figure above.

Usually register REGX is called the "active register".
Register REGX_BUF is sometimes called the "buffered register". Other terms are the "preload register" and the "shadow register (?)".

The confusion explained.

Unfortunately there is a confusion about the term "shadow register". From what I read on several sources from the internet, it refers to REGX_BUF. But in the reference manual RM0385 from the STM32F746 microcontroller and RM0410 from the STM32F767 microcontroller I stumble on the exact opposite interpretation of this term "shadow register". It would not refer to REGX_BUF, but rather to REGX.
This is a picture from the reference manual:

RM0385 -> chapter 23 General-purpose timers -> 23.3.2 Counter modes -> Fig 199

RM0410 -> Chapter 26 General-purpose timers -> 26.3.2 Counter modes -> Fig 244

This figure confuses me. Do I have a wrong interpretation of the term "shadow register", or is it STMicroelectronics who made an error while writing this reference manual?

Solution

The problem is that the term "shadow register" does not have a specific and architecture-independent meaning.

For example, the ARM architecture has a set of general purpose registers that you can write to and read from (R0 - R12). However, if you enter the interrupt handler context R8 - R12 are switched to "shadow registers." This means that you still address them like you would in a normal program, but you're accessing completely different registers than the R8 - R12 that you used in the normal program. They're dedicated interrupt handling resources so you don't have to deal with saving and restoring registers like you normally would.

Some PIC microcontrollers allowed you to write to and read from the same address for pin I/O, but in reality, you are writing to a separate buffer than you read from, because writing out to the pins may not necessarily change their state immediately. This configuration allowed the architecture to buffer your write request while it waited until it could change the pin state. These extra buffers are also sometimes called shadow registers, and seems similar to your example. Using the terminology given in your examples, I suppose this would be called a "preload register."

In general, the term is used to refer to multiple hardware resources that you can address the same way. Which one of them is the "real" register and which is the "shadow" register is not consistent across architectures and vendors, and in the end is probably not very important either.