AXI4 AxVALID high in same clock

I have been looking for some documentation on the case when ARVALID and AWVALID both go high in the same clock and contain the same address. Should the write be handled first, or should the read? Any help is much appreciated.

AXI4 does not specify this. It is up to you to decide and then to implement this in your interconnect or in your slave.