I want to use rocket chip to generate a axi4crossbar with 2 slave ports and 1 master port, here is my chisel source code
package empty
import chipsalliance.rocketchip.config.{Config, Parameters}
import chisel3._
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.stage.ChiselStage
import chisel3.util.random.FibonacciLFSR
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.amba.axi4._
object myAxiUtil{
val myAXI4MasterParameters = AXI4MasterParameters(name="Axi4Master", id=IdRange(0,3))
val myAXI4MasterPortParameters =Seq(AXI4MasterPortParameters(masters=Seq(myAXI4MasterParameters)))
val myAXI4SlaveParameters1 = AXI4SlaveParameters(
address = Seq(AddressSet(0x80000000L, 0xffff)),
supportsWrite= TransferSizes(64),
supportsRead = TransferSizes(64)
)
val myAXI4SlavePortParameters1 = Seq(AXI4SlavePortParameters(slaves=Seq(myAXI4SlaveParameters1), beatBytes=64))
val myAXI4SlaveParameters2 = AXI4SlaveParameters(
address = Seq(AddressSet(0x90000000L, 0xffff)),
supportsWrite = TransferSizes(64),
supportsRead = TransferSizes(64)
)
val myAXI4SlavePortParameters2 = Seq(AXI4SlavePortParameters(slaves=Seq(myAXI4SlaveParameters2), beatBytes=64))
val myAXI4SlaveParameters3 = AXI4SlaveParameters(
address = Seq(AddressSet(0x00000000L, 0xffffffff)),
supportsWrite = TransferSizes(64),
supportsRead = TransferSizes(64)
)
val myAXI4SlavePortParameters3 = Seq(AXI4SlavePortParameters(slaves=Seq(myAXI4SlaveParameters3), beatBytes=64))
}
//driver
class axi4Driver()(implicit valName:ValName, p:Parameters) extends LazyModule {
import myAxiUtil._
val node = AXI4MasterNode(myAXI4MasterPortParameters)
lazy val module = new LazyModuleImp (this) {
}
override lazy val desiredName = "axi4Driver"
}
//accept
class axi4Accept()(implicit valName:ValName, p:Parameters) extends LazyModule {
import myAxiUtil._
val node = AXI4SlaveNode(myAXI4SlavePortParameters3)
lazy val module = new LazyModuleImp (this) {
}
override lazy val desiredName = "axi4Accept"
}
//top
class xbarTestHarness()(implicit valName:ValName, p:Parameters) extends LazyModule {
import myAxiUtil._
val numSlaves = 2
//two axi4 drivers
val drivers = Seq.fill(numSlaves){
LazyModule(new axi4Driver())
}
//one axi4 accepter
val accept = LazyModule(new axi4Accept())
//axi4 interconnect
val xbar = AXI4Xbar()
//connection
accept.node := xbar
drivers.foreach {d => (xbar := d.node)}
lazy val module = new LazyModuleImp (this) {
}
override lazy val desiredName = "xbarTestHarness"
}
object AxiMain extends App {
println("Generating Hardware")
implicit val p = Parameters.empty
val verilog = (new ChiselStage).emitVerilog(LazyModule(new xbarTestHarness()).module)
}
and I run sbt run, the error is:
[info] running empty.AxiMain
Generating Hardware
Exception in thread "sbt-bg-threads-1" java.lang.ExceptionInInitializerError
at empty.axi4Driver.<init>(crossbar.scala:80)
at empty.xbarTestHarness.$anonfun$drivers$1(crossbar.scala:105)
at scala.collection.generic.GenTraversableFactory.fill(GenTraversableFactory.scala:92)
at empty.xbarTestHarness.<init>(crossbar.scala:105)
at empty.AxiMain$.$anonfun$verilog$1(crossbar.scala:129)
at chisel3.Module$.do_apply(Module.scala:53)
at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:35)
at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:771)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at chisel3.internal.Builder$.build(Builder.scala:766)
at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:35)
at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:293)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
at scala.collection.TraversableLike.flatMap(TraversableLike.scala:293)
at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:290)
at scala.collection.AbstractTraversable.flatMap(Traversable.scala:108)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
at scala.collection.immutable.List.foldLeft(List.scala:91)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
at scala.collection.immutable.List.foldLeft(List.scala:91)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.execute(Stage.scala:58)
at chisel3.stage.ChiselStage.emitVerilog(ChiselStage.scala:101)
at empty.AxiMain$.delayedEndpoint$empty$AxiMain$1(crossbar.scala:129)
at empty.AxiMain$delayedInit$body.apply(crossbar.scala:123)
at scala.Function0.apply$mcV$sp(Function0.scala:39)
at scala.Function0.apply$mcV$sp$(Function0.scala:39)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
at scala.App.$anonfun$main$1$adapted(App.scala:80)
at scala.collection.immutable.List.foreach(List.scala:431)
at scala.App.main(App.scala:80)
at scala.App.main$(App.scala:78)
at empty.AxiMain$.main(crossbar.scala:123)
at empty.AxiMain.main(crossbar.scala)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:566)
at sbt.Run.invokeMain(Run.scala:143)
at sbt.Run.execute$1(Run.scala:93)
at sbt.Run.$anonfun$runWithLoader$5(Run.scala:120)
at sbt.Run$.executeSuccess(Run.scala:186)
at sbt.Run.runWithLoader(Run.scala:120)
at sbt.Defaults$.$anonfun$bgRunTask$6(Defaults.scala:1980)
at sbt.Defaults$.$anonfun$termWrapper$2(Defaults.scala:1919)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at scala.util.Try$.apply(Try.scala:213)
at sbt.internal.BackgroundThreadPool$BackgroundRunnable.run(DefaultBackgroundJobService.scala:369)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
at java.base/java.lang.Thread.run(Thread.java:829)
Caused by: java.lang.IllegalArgumentException: requirement failed
at scala.Predef$.require(Predef.scala:268)
at freechips.rocketchip.amba.axi4.AXI4SlaveParameters.$anonfun$new$1(Parameters.scala:23)
at freechips.rocketchip.amba.axi4.AXI4SlaveParameters.$anonfun$new$1$adapted(Parameters.scala:23)
at scala.collection.immutable.List.foreach(List.scala:431)
at freechips.rocketchip.amba.axi4.AXI4SlaveParameters.<init>(Parameters.scala:23)
at empty.myAxiUtil$.<init>(crossbar.scala:60)
at empty.myAxiUtil$.<clinit>(crossbar.scala)
... 81 more
I can not find out the reason leading the error. Maybe the imp of driver and accept must not be empty?
However, if I want to use the rocketchip library to generate the axicrossbar verilog module with some custom paramters(such as addrWidh, dataWidth), is there any other solution?
yes, I have found that therer is an parameters error for AXI4SlaveParameters, the second argument of AddressSet() must also be a BigInt which is end with "L"