[SOLVED] Accessing Verilog genvar generated instances in simulation code

Accessing Verilog genvar generated instances in simulation code

This is a Verilog releated question. I am working with XILINX ISE as a dev environment.

I am trying to access variables in the simulation that are automatically generated using genvar but I am receiving the following error -> HDLCompiler:71

Problem Example:

genvar i;

generate

for(i=0; i < N; i=i+1)

begin:Sys_Modules

  TypeXModule #(.width(10)) xmod(.dataY(dataY)));

end

endgenerate

When I ran synthesis or simulation I can see that Sys_Modules[0..N-1].xmod instances are created.

When I try to add a line to the simulation accessing the Sys_Modules array:

Sys_Modules[i].xmod.dataY

I get the following error:

HDLCompiler:71 dataY is not declared under prefix xmod

Is there any way to access automatically generated values in the simulation?

Thanks!

Solution

It is legal to write a hierarchical reference to a generated instance. The functionality is described in sections 2.7.2 and 12.1.3 of the IEEE Verilog standard. However, the instance subscript must be a constant so that it can be resolved at compile time.