In RISC-V, why setting the `rl` bit on the LR instruction isn't necessary to make the LR/SC sequence sequentially consistent?

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA says:

Setting the aq bit on the LR instruction, and setting both the aq and the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart.

My question is: what prevents earlier memory operations from being reordered after lr.aq, breaking the sequential consistency guarantee, if the rl bit isn't set on the lr instruction? Shouldn't it be lr.aqrl instead?

The specification has been improved regarding this: https://github.com/riscv/riscv-isa-manual/issues/886