Why aren’t opcode and funct7 and funct3 a single 17-bit field?
In RISC-V, I want to know why opcode and funct7 and funct3 don't get together to be a 17-bits field?
RISC V has 6 different instruction formats for 32-bit instructions. All formats share the opcode field, and the opcode field is used to determine the instruction size and instruction format.
While some of the other fields are shared between two or more formats, no other field is present in all formats.
For example, the funct7 field is only present in one of the six formats for 32-bit instructions, namely the register/register instruction format.
The funct3 field is present in 4 of the 6 formats for 32-bit instructions, but not all formats.
I want to know why opcode and funct7 and funct3 don't get together to be a 17-bits field?
Since these two other fields are essentially specific only to a subset of instructions / instruction formats, they really cannot be considered part of the opcode in the general case. When the format is register/register, then all three of those fields together determine the operation to be performed.
We can extract all three fields simultaneously, though; however, we would have to be aware that such an extraction would only be applicable when the instruction is of the right format.
In fact, this is how the hardware generally works: it starts decoding fields even before it knows which fields are applicable to this particular instruction. After this initial, overly broad decoding takes place, other hardware selects which of the fields to use and how, ignoring other computations that were done just in case the instruction was actually different.
For example, the hardware will likely be extracting the 5-bit fields rs2 and rs1, using those as indexes into the register file to obtain values from those registers and make them ready for computation, regardless of the actual instruction format. This, then, is wasted work when the instruction doesn't have these fields, but doing that work before knowing the opcode speeds things up when these fields are applicable. Other parts of the hardware are extracting immediate values, and all this is begin done in parallel for performance.
Here are all the 32-bit formats in one image:
- How are interrupts handled when interrupts are disabled?
- RISC-V U-Format instruction immediate confusion
- Why is RISC-V GCC uselessly reserving stack space in a function that returns a small struct?
- GCC Linker error relocation error in RISCV 64 bit
- How do machine read the instructions of Risc-v
- Why aren’t opcode and funct7 and funct3 a single 17-bit field?
- How to fix "unsafe attribute used without unsafe" in custom attribute macro?
- Is mulw faster than mul on riscv 64-bit platforms?
- RISCV sleep (wfi) and interrupts
- Chisel Passing Enum type as IO
- RISCV assembly 32bit multiplication without MUL giving incorrect result
- raise Store/AMO page fault when trying write stack in xv6's trampoline
- Discrepancy of `unsigned long` size between llvm and gcc in riscv32
- Why is JALR used instead of JAL for returning from subroutines
- Running test on Rocket core CPU - global variable initialized to 0 is unsuccessful, output wrong value instead
- GNU RISC-V Embedded GCC throws "x ISA extension `xw' must be set with the versions" error
- How to set RISC-V `-march` for zig build
- Qemu RiscV bare metal set SATP register failed
- Vexriscv - implement ram as block ram
- What kind of executable is produced by gcc wtih `-static-pie`?
- What is necessary in the RISC-V boot process?
- Is this inline RISC-V Rust assembly correct?
- Why won't my linker put .rodata after .text?
- Are programs compiled for RV32E guaranteed to produce equivalent results on RV32I machines?
- How to change the gem5 RVV vector length
- Why encode RISCV PseudoInstruction LI to four instructions instead of two?
- Zig cross-compiling riscv64-linux-musl fails on Windows
- I want to write an RISC-V assembly code that removes zeros from the given array and stores in the same exact memory address
- Error Fetching Submodule in RISC-V GNU Toolchain: Server Does Not Allow Request for Unadvertised Object
- Programming with RISC-V: how to write cleaner, less ugly code for the Collatz conjecture?