I am trying to work on Rocketchip simulation with Verilator that comes within the Rocket Chip Generator repo. From my understanding, Verilator will first take the scala files (in ./src/main/scala/) and translate them into verilog files (in ./emulator/generated-src) that represents the Rocketchip core's structure, then use the verilog files with a verilog testbench (I suppose it is the TestDriver.v in ./src/main/resources/vsrc/) to convert to C/C++ and to generate an executable. Finally, this executable will include another binary executable that is converted from a C program (for example helloworld.c) using GCC.
If this makes sense, the testbench TestDriver.v is completely merged with the executable, and cannot be freely edited. If I ever edited it, I will have to re-make the emulator project.
I am not sure whether my understanding is true or not - if it is true, is it possible to edit testbench without re-make the project? If it is wrong, what is the testbench file for the verilator simulation?
Besides, is there a way to include the C program from the testbench (using something like $readmemh) instead of the executable? If so, how to?
I have tried to look through many online resources including StackOverflow, Github issues, Google Community etc, but still cannot solve my question. Any help will be appreciated!
Thank you very much!!
Actually verilator does not take scala file and not translate it to verilog. That is a role of FIRRTL and chisel compiler.
As you know, the rocketchip is designed with chisel. The chisel is a sort of scala library for designing hardware. The chisel code as rocketchip can translate to verilog through firrtl.
After you generate verilog from the chisel, you can run rtl simulation with verilator or something else(vcs, xecilum, ...)
The TestDriver.v is a tb top for the vcs, xecilum, and etc.
~/src/main/resources/csrc/emulator.cc is a tb top for verilator. Since tb top for verilator should be a c++ or systemC.