riscvverilator

How to run testbench.v with verilator

I found a RISCV project on GitHub(here is the project), and tried to run a testbench.v file of this project with verilator. However, I encountered an error during the process.

My Workspace is:

../
├── CHIP.v
├── README.md
├── VCPU.v
├── WIN.sdf
├── WIN.v
├── WIN_syn.v
├── area_CPU.out
├── sim
│   ├── Makefile
│   ├── dat
│   │   ├── Fibonacci_instruction.txt
│   │   ├── Foutput.txt
│   │   ├── golden.dat
│   │   └── instruction2.txt
│   ├── include
│   │   ├── add.h
│   │   └── verilated.h
│   └── src
│       └── testbench.v
├── src
│   ├── ALU.v
│   ├── ALU_Control.v
│   ├── Adder.v
│   ├── CPU.v
│   ├── Control.v
│   ├── DataMemory.v
│   ├── EX_MEM.v
│   ├── ForwardingMUX.v
│   ├── ForwardingUnit.v
│   ├── HazardDetect.v
│   ├── ID_EX.v
│   ├── IF_ID.v
│   ├── Instruction_Memory.v
│   ├── MEM_WB.v
│   ├── MUX32.v
│   ├── MUX_Control.v
│   ├── PC.v
│   ├── Registers.v
│   ├── Sign_Extend.v
│   ├── VALU.v
│   ├── VALU_ctrl.v
│   ├── VControl.v
│   ├── VEX_MEM.v
│   └── shift2.v
└── syn.src

I cloned the project and wrote a Makefile :

TOP_NAME := CPU
SRC_DIR  := ../src/
SRC_FILE := $(shell find $(SRC_DIR) -name '*.vh') $(shell find $(SRC_DIR) -name '*.svh') $(shell find $(SRC_DIR) -name '*.v') $(shell find $(SRC_DIR) -name '*.sv')

.PHONY: run clean

obj_dir/V$(TOP_NAME): src/* $(SRC_FILE)
    verilator -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v $(SRC_FILE) -I$(SRC_DIR) --top $(TOP_NAME) -j `nproc`

run: obj_dir/V$(TOP_NAME)
    ./obj_dir/V$(TOP_NAME)

clean:
    rm -rf obj_dir

After that, when I entered make in the terminal attempting to compile the files, an error occurred:

verilator -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v   ../src/shift2.v ../src/Instruction_Memory.v ../src/EX_MEM.v ../src/ForwardingUnit.v ../src/Registers.v ../src/CPU.v ../src/ForwardingMUX.v ../src/VEX_MEM.v ../src/VALU_ctrl.v ../src/HazardDetect.v ../src/MEM_WB.v ../src/IF_ID.v ../src/VALU.v ../src/ALU.v ../src/DataMemory.v ../src/MUX32.v ../src/Control.v ../src/Adder.v ../src/ID_EX.v ../src/VControl.v ../src/PC.v ../src/MUX_Control.v ../src/Sign_Extend.v ../src/ALU_Control.v  -I../src/ --top CPU -j `nproc`
make[1]: Entering directory '/home/chris/Code/graduation-project/sim/obj_dir'
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VCPU.cpp VCPU___024root__DepSet_h6c062b6c__0.cpp VCPU___024root__DepSet_h295dba0a__0.cpp VCPU__Trace__0.cpp VCPU__ConstPool_0.cpp VCPU___024root__Slow.cpp VCPU___024root__DepSet_h6c062b6c__0__Slow.cpp VCPU___024root__DepSet_h295dba0a__0__Slow.cpp VCPU__Syms.cpp VCPU__Trace__0__Slow.cpp > VCPU__ALL.cpp
echo "" > VCPU__ALL.verilator_deplist.tmp
ccache g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++17 -Os -c -o VCPU__ALL.o VCPU__ALL.cpp
Archive ar -rcs VCPU__ALL.a VCPU__ALL.o
g++    verilated.o verilated_vcd_c.o VCPU__ALL.a      -o VCPU
/usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/11/../../../x86_64-linux-gnu/Scrt1.o: in function `_start':
(.text+0x1b): undefined reference to `main'
collect2: error: ld returned 1 exit status
make[1]: *** [VCPU.mk:61: VCPU] Error 1
rm VCPU__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/chris/Code/graduation-project/sim/obj_dir'
%Error: make -C obj_dir -f VCPU.mk -j 20 exited with 2
%Error: Command Failed /usr/local/bin/verilator_bin -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP -exe --trace --trace-structs --build --timing src/testbench.v ../src/shift2.v ../src/Instruction_Memory.v ../src/EX_MEM.v ../src/ForwardingUnit.v ../src/Registers.v ../src/CPU.v ../src/ForwardingMUX.v ../src/VEX_MEM.v ../src/VALU_ctrl.v ../src/HazardDetect.v ../src/MEM_WB.v ../src/IF_ID.v ../src/VALU.v ../src/ALU.v ../src/DataMemory.v ../src/MUX32.v ../src/Control.v ../src/Adder.v ../src/ID_EX.v ../src/VControl.v ../src/PC.v ../src/MUX_Control.v ../src/Sign_Extend.v ../src/ALU_Control.v -I../src/ --top CPU -j 20
make: *** [Makefile:8: obj_dir/VCPU] Error 2

This appears to be a compilation issue, but I'm unsure how to resolve it. Can anyone advise on what steps to take? My verilator version is Verilator 5.002 2022-10-29 rev v5.002

Solution

  • (@FabienM, Thank you for your response!)

    Upon reviewing the Verilator guidebook, I discovered that the latest Verilator now supports testbench Verilog through the addition of the --timing argument. Consequently, it suffices for me to author a concise C++ file to serve as the entry point via a main function. Below is the updated Makefile I've devised:

    TOP_NAME := testbench
SRC_DIR  := ../src
SRC_FILE := $(shell find $(SRC_DIR) -name '*.vh') $(shell find $(SRC_DIR) -name '*.svh') $(shell find $(SRC_DIR) -name '*.v') $(shell find $(SRC_DIR) -name '*.sv')

.PHONY: run clean

obj_dir/V$(TOP_NAME): src/* $(SRC_FILE)
    verilator -cc -Wno-NULLPORT -Wno-COMBDLY -Wno-PINMISSING -Wno-MODDUP --exe --trace --trace-structs --build --timing  src/sim_main.cpp $(SRC_FILE) -I$(SRC_DIR) --top $(TOP_NAME)   -j `nproc`

run: obj_dir/V$(TOP_NAME)
    ./obj_dir/V$(TOP_NAME)

clean:
    rm -rf obj_dir

    My sim_main.cpp is：

    #include <verilated.h>
#include "verilated_vcd_c.h"
#include "Vtestbench.h"

int main(int argc, char **argv)
{
    // Construct context object, design object, and trace object
    VerilatedContext *m_contextp = new VerilatedContext; // Context
    VerilatedVcdC *m_tracep = new VerilatedVcdC;         // Trace
    Vtestbench *m_duvp = new Vtestbench;                 // Design
    // Trace configuration
    m_contextp->traceEverOn(true);     // Turn on trace switch in context
    m_duvp->trace(m_tracep, 3);        // Set depth to 3
    m_tracep->open("cnt_ceil_wf.vcd"); // Open the VCD file to store data
    // Write data to the waveform file
    while (!m_contextp->gotFinish())
    {
        // Refresh circuit state
        m_duvp->eval();
        // Dump data
        m_tracep->dump(m_contextp->time());
        // Increase simulation time
        m_contextp->timeInc(1);
    }
    // Remember to close the trace object to save data in the file
    m_tracep->close();
    // Free memory
    delete m_duvp;
    return 0;
}

    Now run the makefile so I can simulate it correctly!

    enter image description here