I'm getting an error while running implementation in Vivado. This is my top level module:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Single Cycle ARM Processor
entity Processor is
port (
CLK : in STD_LOGIC;
reset : in STD_LOGIC;
Instr : out STD_LOGIC_VECTOR(31 downto 0);
PC : out STD_LOGIC_VECTOR(31 downto 0);
ALUResult : out STD_LOGIC_VECTOR(31 downto 0);
WriteData : out STD_LOGIC_VECTOR(31 downto 0);
Result : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture Struct of Processor is
component ControlUnit is
port (
Instr : in STD_LOGIC_VECTOR(31 downto 0);
Flags : in STD_LOGIC_VECTOR(3 downto 0);
RegSrc : out STD_LOGIC_VECTOR(2 downto 0);
ALUSrc : out STD_LOGIC;
ImmSrc : out STD_LOGIC_VECTOR(1 downto 0);
ALUCtrl : out STD_LOGIC_VECTOR(2 downto 0);
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemWrite : out STD_LOGIC;
FlagsWrite : out STD_LOGIC_VECTOR(1 downto 0);
PCSrc : out STD_LOGIC
);
end component;
component Datapath is
generic (
INSTMEM_SIZE: POSITIVE := 6; -- Instruction memory addressable bytes
DATAMEM_SIZE: POSITIVE := 5 -- Data memory addressable bytes
);
port (
CLK, reset : in STD_LOGIC;
RegSrc : in STD_LOGIC_VECTOR( 2 downto 0);
ALUSrc : in STD_LOGIC;
ImmSrc : in STD_LOGIC_VECTOR( 1 downto 0);
ALUCtrl : in STD_LOGIC_VECTOR( 2 downto 0);
MemtoReg : in STD_LOGIC;
RegWrite : in STD_LOGIC;
MemWrite : in STD_LOGIC;
FlagsWrite : in STD_LOGIC_VECTOR( 1 downto 0);
PCSrc : in STD_LOGIC;
Instr : out STD_LOGIC_VECTOR(31 downto 0);
Flags : out STD_LOGIC_VECTOR( 3 downto 0);
PC : out STD_LOGIC_VECTOR(31 downto 0);
ALUResult : out STD_LOGIC_VECTOR(31 downto 0);
WriteData : out STD_LOGIC_VECTOR(31 downto 0);
Result : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal Instr_in: STD_LOGIC_VECTOR(31 downto 0);
signal Flags: STD_LOGIC_VECTOR(3 downto 0);
signal RegSrc: STD_LOGIC_VECTOR(2 downto 0);
signal ALUSrc: STD_LOGIC;
signal ImmSrc: STD_LOGIC_VECTOR(1 downto 0);
signal ALUCtrl: STD_LOGIC_VECTOR(2 downto 0);
signal MemtoReg: STD_LOGIC;
signal RegWrite: STD_LOGIC;
signal MemWrite: STD_LOGIC;
signal FlagsWrite: STD_LOGIC_VECTOR(1 downto 0);
signal PCSrc: STD_LOGIC;
constant INSTMEM_SIZE: POSITIVE := 6; -- Instruction memory addressable bytes
constant DATAMEM_SIZE: POSITIVE := 5; -- Data memory addressable bytes
begin
ctrl_unit: ControlUnit port map (
Instr_in, Flags,
RegSrc, ALUSrc, ImmSrc, ALUCtrl, MemtoReg,
RegWrite, MemWrite, FlagsWrite,
PCSrc
);
data_path: Datapath generic map (INSTMEM_SIZE, DATAMEM_SIZE)
port map (
CLK, reset,
RegSrc, ALUSrc, ImmSrc, ALUCtrl, MemtoReg,
RegWrite, MemWrite, FlagsWrite, PCSrc,
Instr_in, Flags, PC, ALUResult, WriteData, Result
);
Instr <= Instr_in;
end;
This is the error I'm getting:
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced IO Ports (161) is greater than number of available sites (150).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 150 sites available on device, but needs 160 sites.
Term: ALUResult[0]
Term: ALUResult[1]
Term: ALUResult[2]
Term: ALUResult[3]
Term: ALUResult[4]
Term: ALUResult[5]
Term: ALUResult[6]
Term: ALUResult[7]
Term: ALUResult[8]
Term: ALUResult[9]
Term: ALUResult[10]
Term: ALUResult[11]
Term: ALUResult[12]
Term: ALUResult[13]
Term: ALUResult[14]
Term: ALUResult[15]
Term: ALUResult[16]
Term: ALUResult[17]
Term: ALUResult[18]
Term: ALUResult[19]
Term: ALUResult[20]
Term: ALUResult[21]
Term: ALUResult[22]
Term: ALUResult[23]
Term: ALUResult[24]
Term: ALUResult[25]
Term: ALUResult[26]
Term: ALUResult[27]
Term: ALUResult[28]
Term: ALUResult[29]
Term: ALUResult[30]
Term: ALUResult[31]
Term: Instr[0]
Term: Instr[1]
Term: Instr[2]
Term: Instr[3]
Term: Instr[4]
Term: Instr[5]
Term: Instr[6]
Term: Instr[7]
Term: Instr[8]
Term: Instr[9]
Term: Instr[10]
Term: Instr[11]
Term: Instr[12]
Term: Instr[13]
Term: Instr[14]
Term: Instr[15]
Term: Instr[16]
Term: Instr[17]
Term: Instr[18]
Term: Instr[19]
Term: Instr[20]
Term: Instr[21]
Term: Instr[22]
Term: Instr[23]
Term: Instr[24]
Term: Instr[25]
Term: Instr[26]
Term: Instr[27]
Term: Instr[28]
Term: Instr[29]
Term: Instr[30]
Term: Instr[31]
Term: PC[0]
Term: PC[1]
Term: PC[2]
Term: PC[3]
Term: PC[4]
Term: PC[5]
Term: PC[6]
Term: PC[7]
Term: PC[8]
Term: PC[9]
Term: PC[10]
Term: PC[11]
Term: PC[12]
Term: PC[13]
Term: PC[14]
Term: PC[15]
Term: PC[16]
Term: PC[17]
Term: PC[18]
Term: PC[19]
Term: PC[20]
Term: PC[21]
Term: PC[22]
Term: PC[23]
Term: PC[24]
Term: PC[25]
Term: PC[26]
Term: PC[27]
Term: PC[28]
Term: PC[29]
Term: PC[30]
Term: PC[31]
Term: Result[0]
Term: Result[1]
Term: Result[2]
Term: Result[3]
Term: Result[4]
Term: Result[5]
Term: Result[6]
Term: Result[7]
Term: Result[8]
Term: Result[9]
Term: Result[10]
Term: Result[11]
Term: Result[12]
Term: Result[13]
Term: Result[14]
Term: Result[15]
Term: Result[16]
Term: Result[17]
Term: Result[18]
Term: Result[19]
Term: Result[20]
Term: Result[21]
Term: Result[22]
Term: Result[23]
Term: Result[24]
Term: Result[25]
Term: Result[26]
Term: Result[27]
Term: Result[28]
Term: Result[29]
Term: Result[30]
Term: Result[31]
Term: WriteData[0]
Term: WriteData[1]
Term: WriteData[2]
Term: WriteData[3]
Term: WriteData[4]
Term: WriteData[5]
Term: WriteData[6]
Term: WriteData[7]
Term: WriteData[8]
Term: WriteData[9]
Term: WriteData[10]
Term: WriteData[11]
Term: WriteData[12]
Term: WriteData[13]
Term: WriteData[14]
Term: WriteData[15]
Term: WriteData[16]
Term: WriteData[17]
Term: WriteData[18]
Term: WriteData[19]
Term: WriteData[20]
Term: WriteData[21]
Term: WriteData[22]
Term: WriteData[23]
Term: WriteData[24]
Term: WriteData[25]
Term: WriteData[26]
Term: WriteData[27]
Term: WriteData[28]
Term: WriteData[29]
Term: WriteData[30]
Term: WriteData[31]
Resolution: Consider using Xilinx part with greater number of IO pins
ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 50 | 1 | LVCMOS33(1) | | | +3.30 | YES | |
| 33 | 50 | 0 | | | | | | |
| 34 | 50 | 0 | | | | | | |
| 35 | 50 | 0 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 200 | 1 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 13 | CLK | LVCMOS33 | IOB_X0Y26 | Y9 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1349a576a
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2665.531 ; gain = 0.000 ; free physical = 138 ; free virtual = 2287
Phase 1 Placer Initialization | Checksum: 1349a576a
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2665.531 ; gain = 0.000 ; free physical = 138 ; free virtual = 2287
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 1349a576a
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2665.531 ; gain = 0.000 ; free physical = 138 ; free virtual = 2287
INFO: [Common 17-83] Releasing license: Implementation
44 Infos, 0 Warnings, 100 Critical Warnings and 5 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Wed Mar 27 17:52:20 2024...
This is my constraints file:
# CLK - Zedboard 100MHz oscillator
set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports {CLK}]
# define clock and period
create_clock -period 10 -name CLK -waveform {0.000 5.000} [get_ports {CLK}]
set_property IOB TRUE [all_outputs]
And the card I'm using is Zynq 7000 ZC702 Evaluation Board (xc7z020clg484-1) which is supposed to have 200 available IOBs. I suppose it has to do something with the placement of the clock. I do not understand much about the format of the constraints file. Any help is appreciated.
This is my answer to the posted question
For the PL design, every io pin needs one io_standard and one package_pin constraint. You have many unconstrained pins. You need an example constraints file to base your design's constraints file on.
Search 'zynq zc702 evaluation board constraints'.
It looks like there are several ways to get example constraints files including github, AMD's site, and within the tool.
I found one by going to AMD, then near the bottom of the page
resources->document type -> board files -> zc702-ucf-xdc-rdf0173-rev3-0.zip.
You have to log in to the AMD site for file access/download.
Also take care that the names in your top level module match the names used in the constraints file.
This is additional info based on the posted code, the idea that you have a Verilog ARM model targeting the Zynq PL, and and the comment that you do not know how to use constraints.
Constraints are used to map/define-the-interface/connect ports on your Verilog RTL top level fpga pins
CLK : in STD_LOGIC;
reset : in STD_LOGIC;
Instr : out STD_LOGIC_VECTOR(31 downto 0);
PC : out STD_LOGIC_VECTOR(31 downto 0);
ALUResult : out STD_LOGIC_VECTOR(31 downto 0);
WriteData : out STD_LOGIC_VECTOR(31 downto 0);
Result : out STD_LOGIC_VECTOR(31 downto 0)
to other electronic components on the host printed circuit board.
Use the board schematic to determine the pin numbers of the board peripheral that needs to be interfaced to.
There is an example in the original post
set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports {CLK}]
This is saying "My board has a 3.3V LVCMOS oscillator connecting to the fpga on pin Y9 connect my signal 'CLK' to that pin"
You need to provide the same constraints for each port on you top level. Use the schematic to determine what pins the peripherals need to be connected to.
Looking at the board's web page, I don't know what board peripheral you want to interface to using the top level IOs Instr, PC and its other busses/bits. Also, it does not make a lot of sense to have Verilog model for an ARM processor synthesized into the Zynq PL. The typical use of the ARM on Zynq is the hard IP located in the PS section, which is accessed in the PL/Verilog using AXI busses. Maybe the design intent is to interface to something on the FMC connector. If so then the pastbin file provided the pin numbers for doing so. If that is not the case then you might want to read some Zynq tutorial material like 'The Zynq Book' (free download) or just search 'Zynq processor tutorial' to learn how to implement an ARM processor in Zynq.
The normal design flow for the basic ARM processor on Zynq, involves creating Xilinx IP Integrator diagrams to specify connections, parameters, memory map for the Zync (memory, timers, SPI, RAM, ROM etc). Its not Verilog. You can write peripherals in Verilog and connect to the ARM PS subsystem thru AXI busses.
If this is you first time targeting physical hardware with fpga, I would start with a simple design using dipswitches to light LED's, and get that working all the way thru lab deployment, rather than deploying a ARM processor design.