This answer is somewhat related but doesn't really answer my question: How do you force a makefile to rebuild a target?

I have the following targets defined in a Makefile:

dist-3:
        @echo "calling dist-3"

dist-2: dist-3
        @echo "calling dist-2"

dist-1: dist-2 dist-3
        @echo "calling dist-1"

The output of 'make dist-1' is:

calling dist-3
calling dist-2
calling dist-1

but I want dist-3 to be executed multiple times. I've tried declaring dist-3 as .PHONY and tried using the FORCE option but neither seem to work.

Is there a way to have dist-3 executed multiple times?

You can achieve this by recursively calling make using the MAKE variable within the target recipes. Since these targets aren't referencing files, you should declare them as .PHONY.

Makefile

.PHONY: dist-3
dist-3:
    @echo "calling dist-3"

.PHONY: dist-2
dist-2:
    @$(MAKE) --no-print-directory dist-3
    @echo "calling dist-2"

.PHONY: dist-1
dist-1:
    @$(MAKE) --no-print-directory dist-2 dist-3
    @echo "calling dist-1"

$ make dist-1
calling dist-3
calling dist-2
calling dist-3
calling dist-1