How does the LDA instruction interact with RAM and IR on MU1 architecture?

I am trying to understand this LDA instruction.

After the fetch instruction, IR holds LDA S.

1 - In the first step, DIN = [IR], IR is supposed to be interpreted as an address (because of the brackets), but it holds an instruction, how is that supposed to happen?

2 - The path to the address multiplexer, where does it go? In another diagram, it goes to RAM, what's happening there? Does it create a new register holding that address?

3 - After that, how does DIN gets the content from that address? shouldn't there be some sort of another instruction?

I understand what every part does, and frankly I understand the diagram below as a concept, but I think what I am missing is what's happening beyond it, the three Data out / Address / Data in I am confused to what they point out / do, what's happening in their background?

The interface to memory generally consists of an address bus, and a data bus, and, two control lines/signals.  One control signal to make memory do a read and the other to make it do a write.

The width of the address bus indicates how much memory the architecture can address/have.  The width of the data bus indicates the size of each individual memory location.

The general principle of memory is that the last value written to each specific address is the value that is retrieved upon read (of that same address).  In other words, each address stores a value that is remembered until changed by another write to that address.

Because programs are too large to fit in the CPU directly, code instructions (as well as data) are stored in memory.  This means that each instruction in a program has its own unique memory address.

On your diagram, the data bus is split in two parts, an "out" and an "in", but on many architectures data "out" and data "in" share a single data bus.  This sharing works because the processor will only issue read or write (or neither) but never both at the same time.

So, to execute an LDA instruction, first, it is going to put the value of the PC (program counter) onto the address bus, and signal memory to do a read operation.  The processor will direct the newly read data to the IR register for instruction decode.  (The processor will also increment the PC so that the next sequential instruction in memory executes after this one.)

Because the fetched instruction is an LDA instruction, an address, S, which is the lower 12 bits of the instruction itself, becomes an address from which to read memory.  So, the lower 12 bits of IR are sent to the address bus, and a read is signaled.  That yields a data in value, which is transferred to the A register.

The processor is now ready for the next instruction, and, the program has some new value in the A register.

On some processors the data bus (here both in & out) and the address bus are "buffered" by registers.  This has to do with the timing of the memory interface, and what specifically happens as the clock steps forward through the various cycles during read and write operations.