I am debugging a simple program that prints the string "Hello, world!" three times. In the information about the registers that the gdb program gives, with the command info register, appear the registers k0, k1, k3, ... k7.
The native architecture of my processor is x86 64-bit.
They're AVX-512 SIMD mask registers, 64 bits each on CPUs with AVX-512BW.
(Otherwise only 16 bits on Xeon Phi, the only CPUs to have AVX-512F without AVX-512BW.)
They don't exist on CPUs without AVX-512.
https://en.wikipedia.org/wiki/AVX-512#Opmask_registers
Merge-masking instructions like vpaddb ymm0{k1}, ymm1, ymm2 keep the old value of YMM0 in elements where the mask register had a 0 bit.
Zero-masking instructions like vpaddb ymm0{k1}{z}, ymm1, ymm2 zero those elements, so no input dependency on the old value of ymm0.
k0 isn't usable for actual masking of other operations (its register-number means no masking in that context). It is usable as a destination or as a normal source for instructions like kxnor k1, k0, k0 to set k1 to all-ones (e.g. before using it as a scatter or gather mask), or like vpcmpltd k0, zmm0, zmm1 / vpmovm2d zmm2, k0 (to emulate SSE2/AVX2-style compare-into-vector, which you'd normally try to avoid with AVX-512. Or if working with 128 or 256-bit vectors, just use the AVX2 instruction unless you need e.g. unsigned-less or greater compare which only AVX-512 has.)
For more details and example uses, see
When using a mask register with AVX-512 load and stores, is a fault raised for invalid accesses to masked out elements? - masked loads/stores do indeed suppress faults for masked elements (where the corresponding k bit is 0).
What is the "correct" way to go from avx/sse masks to avx512 masks?
AVX-512 and Branching (doing stuff based on per-element conditions, which actually needs to be branchless to vectorize well. Masking built into other instructions makes that even more efficient than doing it manually the SSE/AVX way.)
How to generate an AVX-512 mask based on multiple comparisons of FP values in corresponding elements of vectors? - you can combine multiple conditions with masked compare-into-mask.
Fun fact: Intel renames k mask registers using the same register file as x87/MMX registers. https://travisdowns.github.io/blog/2020/05/26/kreg2.html
https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html - Intel documentation for x86-64 includes a description of all registers, for next time you wonder about some new kind of register like bnd0 to bnd3 on a CPU with MPX. (e.g. Skylake. Dropped from later CPUs, but IDK if debuggers and kernels will drop support for it or not.)
https://stackoverflow.com/tags/x86/info - the tag wiki has lots of links to guides and docs in general, definitely worth checking out as a beginner.
Also, a web search for "x86 register k0" finds several pages that would point you in the right direction toward AVX-512: