I wonder if Intel (and Intel compatible) CPUs have an instruction (for diagnostic/debugging purposes) which, for a given linear address, returns the result of paging translation (i.e. the corresponding physical address).
No, it doesn't. I'm not aware of AMD or Via or other x86-64 vendors having one either.
Bochs's built-in debugger probably does, though; it can print some stuff about page tables.
Note that 32-bit mode with PAE would need a 2-register result for such an instruction if it existed.
Also, architects only use up precious opcode coding-space on instructions that will make some important or common real-world code run faster, and same for spending extra transistors to implement it in the decoders and execution units of every CPU.