How to understand which SystemVerilog is supported by Cadence XMVLOG compiler?

I need to move my SV simulation environment from Questa to Xcelium 20.9. I'm facing problems compiling my files with xmvlog, while there are no issues with vlog.

So here's what I did.

1. Make sure the toolchain is correctly installed: I ran this simple example from edaplayground. It works fine. I am also able to see the waves in Simvision

2. Try out a more complex design, which includes some classes and packages.

Here's where I'm not able to proceed: I fail to compile a package. I tried to simplify the file and extract a minimal non-working example.

The file looks like this:

package test_pkg;
  task wait (ref logic clock, int cycl_num);
    for (int k = 0; k < cycl_num; k++) begin
      @(posedge clock);
    end
  endtask : wait
endpackage

So, simple package with one task. Running xrun test/test_pkg.sv:

Lots of errors here. One thing I noticed is that adding void at the beginning of the task declaration solves a few of them.

With that done, the output is:

The problem is in the task definition, as I am able to compile if it is removed.

I also tried the following options for xmvlog

-sv Force SystemVerilog compilation
-sysv2005 Only enable SV-2005 and earlier keywords
-sysv2009 Only enable SV-2009 and earlier keywords

But no luck. Any idea what is wrong here? How do I specify the right SystemVerilog version?

The problem is with your code, not with the Cadence simulator.

One problem is that wait is a Verilog keyword, and it should not be used as a task name. Refer to IEEE Std 1800-2017, section 9.4 Procedural timing controls; it is also part of the 1364 Std. Questa should have given you an error.

You need to change the name to something else, like wait_clk. You need to change it after the endtask keyword as well.

Another problem is that Cadence also gives me errors using ref.

  task wait_clk (ref logic clock, int cycl_num);
                               |
xmvlog: *E,REFANA : reference argument is illegal inside static task-function declaration.
  task wait_clk (ref logic clock, int cycl_num);
                                             |
xmvlog: *E,REFANA : reference argument is illegal inside static task-function declaration.

I don't think you need these inputs to be references. If that is the case, then you can simply remove it:

package test_pkg;
  task wait_clk (logic clock, int cycl_num);
    for (int k = 0; k < cycl_num; k++) begin
      @(posedge clock);
    end
  endtask : wait_clk
endpackage

However, if you do want a ref, you can get more details using nchelp:

nchelp xmvlog REFANA
xmhelp: 20.09-s009: (c) Copyright 1995-2021 Cadence Design Systems, Inc.
xmvlog/REFANA =
    A SystemVerilog reference argument, declared in the formal argument list
    of a task or function, must always be an automatic variable.  The enclosing
    task or function declaration must therefore use the 'automatic' keyword
    to promote all of its formal arguments into automatic variables.

If you just want clock to be a ref:

package test_pkg;
  task automatic wait_clk (ref logic clock, input int cycl_num);
    for (int k = 0; k < cycl_num; k++) begin
      @(posedge clock);
    end
  endtask : wait_clk
endpackage

You should not use void for a task. Doing so did not really fix anything; it just took the compiler down a different path.