How to change the gem5 RVV vector length

I'm currently trying to simulate a algorithm on a RISCV processor using RVV intrinsics. I want to explore how the performance varies depending on the RVV vector length. I've noticed the RISCV ISA file seems to have a configurable vector length. Unfortunately I cannot seem to change it in my simulation configuration file.

Configuration file:

import m5
from m5.objects import System, SrcClockDomain, VoltageDomain, Root
from m5.objects import RiscvO3CPU, Cache, AddrRange, SEWorkload, Process
from m5.objects import MemCtrl, DDR3_1600_8x8, SystemXBar, L2XBar


class L1Cache(Cache):
    assoc = 2
    tag_latency = 2
    data_latency = 2
    response_latency = 2
    mshrs = 4
    tgts_per_mshr = 20

    def connectCPU(self, cpu):
        raise NotImplementedError

    def connectBus(self, bus):
        self.mem_side = bus.cpu_side_ports


class L1ICache(L1Cache):
    size = '16kB'

    def connectCPU(self, cpu):
        self.cpu_side = cpu.icache_port


class L1DCache(L1Cache):
    size = '64kB'

    def connectCPU(self, cpu):
        self.cpu_side = cpu.dcache_port


class L2Cache(Cache):
    size = '256kB'
    assoc = 8
    tag_latency = 20
    data_latency = 20
    response_latency = 20
    mshrs = 20
    tgts_per_mshr = 12

    def connectCPUSideBus(self, bus):
        self.cpu_side = bus.mem_side_ports

    def connectMemSideBus(self, bus):
        self.mem_side = bus.cpu_side_ports


system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]

system.cpu = RiscvO3CPU()

# Create the L1 caches
system.cpu.icache = L1ICache()
system.cpu.dcache = L1DCache()

# Connect the caches to the CPU
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)

# Connect the CPU to the L2 bus
system.l2bus = L2XBar()

# Connect the L1 caches to the L2 bus
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)

# Connect the L2 cache to the CPU side bus
system.l2cache = L2Cache()
system.l2cache.connectCPUSideBus(system.l2bus)

# Connect the L2 cache to the memory bus
system.membus = SystemXBar()
system.l2cache.connectMemSideBus(system.membus)

# Connect the CPU to the memory bus
system.cpu.createInterruptController()

system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.mem_side_ports

binary = './dct2d_riscv.out'

system.workload = SEWorkload.init_compatible(binary)

process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()

# Run SE mode
root = Root(full_system=False, system=system)
m5.instantiate()

print("Beginning simulation!")
exit_event = m5.simulate()

print('Exiting @ tick {} because {}'
      .format(m5.curTick(), exit_event.getCause()))

I have tried to modify system.cpu.isa.vlen = xxx but get the following error: AttributeError: Not allowed to set vlen on 'VectorParamValue'

I was partly correct in my observation, but to change the vlen option, it had to be done by explicitly initialising the ISA with the RiscvISA() constructor, not by modifying the value in the CPU's ISA object

In the configuration file import the ISA object by:

from m5.objects import RiscvISA

Then initialise the ISA after initialising the CPU:

system.cpu.isa = RiscvISA(vlen=xxx)

This is also the way to change other parameters in RVV such as elen etc.