system-verilog

Setting a starting position for the constraint random solver


class square;
    
    rand bit arr [3][3];
    
    function void pre_randomize();
      arr[0][1] = 1;
      $display ("%p",arr);
    endfunction
       
    constraint ab_c {
      foreach (arr[i,j]) {
        if (arr[i][j] == 1) {
          if (i > 0 && j > 0 && j < 2 && i < 2) { arr[i+2][j-1] == 1;
          }
          else arr[i][j] == 0;
        }
      }
    }

I have a 3x3 array, and I am trying to have a pattern where when arr[0][1] (starting position) is 1, then I would like to go to arr[2][0] as 1. It seems constraint solver set the pre_randomize value arr[0][1] to 0 post randomization. Is that expected?


Solution

  • When the foreach loop reaches arr[0][1], the first if condition is true. However, the 2nd if condition is false because i=0. This means the else condition is executed:

          else arr[i][j] == 0;
    

    This sets arr[0][1] to 0:

          else arr[0][1] == 0;
    

    Your constraint code is hard to understand due to the inconsistent indentation and brace usage.