I wrote a module which used the writing method like:
always_ff@(posedge clk)begin
logic [WIDTH-1:0] signal1;
........
end
When I compiled it in VCS, I drove the signal in testbench, and when I checked the waveform in Verdi, I found that the signal of signal1 was filled with x (unknown value). So I modified the variable declaration and put the variable outside the always block, so that it can work properly.
Therefore, I would like to ask whether IEEE has stated that it is okay to declare temporary variables in the always block, so that I can confirm whether it is a problem with my code or the VCS compiler.
It's certainly legal to declare variables inside a procedural block of code as long as they appear before any procedural statements. (See section 9.3.1 Sequential blocks in the IEEE 1800-2023 SystemVerilog LRM)
There's nothing temporary about it; it all has to do with scope and visibility. In this case you've declared a static variable signal1 inside and unnamed begin/end. It retains its value between each iteration of the always loop. But since the block is unnamed, it's not available for reference outside the block.
A variable’s temporary status depends on whether it’s read or written first inside a sequential always block. Attempting to read a variable before writing to it will retrieve its previous value, indicating a storage element.
To understand why you’re seeing an X value depending on where the variable is declared, you’d need to provide more code and command line compilation options.