In SystemVerilog, to create a custom type based on another type I believe I can use either typedef or localparam type. For example, I believe the following are equivalent:
typedef logic [31:0] T;
localparam type T = logic [31:0];
Am I correct in saying these are equivalent? Do they differ in any way? Are there cases in which one would be used over the other?
What you’ve written is indeed equivalent in functionality. SystemVerilog has a lineage from various sources, and sometimes, these sources converge (for instance, typedefs from C/C++ and parameters from Verilog).
A parameter offers additional functionality compared to a typedef, as it allows for instance-by-instance overriding of the parameter type.