mipspipelinecpu-architecturerisc

Decision making in Pipeline stalls

A load word instruction is immediately followed by a branch instruction(of mips 32).

lw r2, (0)r1;-- I swap registers here as opposed to my previous question
Beq r2, r3, target;

To produce a execution diagram, IF ID EX MEM WB. Now where should the stall be for BEQ

IF ID EX MEM WB
   IF *  *   ID EX

or 

IF ID EX MEM WB
   *  *  IF  ID  EX

I just want to understand if both ways are possible. Also, what hardware manipulation is involved for such stalls?

Solution

  • In the simple pipeline you show, lw is still being decoded while the next insn is being fetched. The pipeline can't tell that they conflict until they're both decoded.

    Think through exactly what your 2nd stall is doing: The CPU delays fetching the next instruction before the current one is even decoded. It doesn't know what either instruction is at this point.

    IF ID EX MEM WB     lw
   *  IF ID  EX     beq  // lw isn't even decoded yet, and neither is this one, so no way to tell if they conflict.

    re: your update: IF isn't an instruction, it's a pipeline stage.

    BTW, the question was much clearer before you removed the pipeline diagrams. You should put them back in, with code formatting (select the text and click the {} icon, or hit ctrl-k.)