Hamming (7,4) Code - Finite State Machine

So I am working on a lab assignment for a Computer Engineering class. I have a assignment due and I am trying to get all the help I can, as for the professor I have to wait until a few days before I can speak with them for help. So I am seeing if I can get help her.

My issue is that my finite state machine is not working how it should be as asked from the lab assignment. The state machine is supposed to have 3 states; idle, s1, s2. Idle is supposed to show all zeros in the waveform, State 1 will show the randomly generated 4-bit number from the LFSR, and State 2 will show the result from the 4-bit number after hamming (7,4) is done. The clock is changed to a 1HZ clock, clk division used.

Code is as follows:

CLOCK_1HZ

    module clock_1hz (clk, reset, clk2);
    input clk, reset;
    output clk2;

    reg temp;
    reg [25:0] cnt;

always @(posedge clk or posedge reset)
    begin
        if (reset)
            begin
                cnt = {25{1'b0}};
            end
        else
            begin
                if (cnt == 26'b10111110101111000001111111)
                    begin
                        cnt = {25{1'b0}};
                        temp = 1'b1;
                    end
                else if (cnt < 26'b01011111010111100000111111)
                    begin
                        cnt = cnt + 1;
                        temp = 1'b1;
                    end
                else
                    begin
                        cnt = cnt + 1;
                        temp = 1'b0;
                    end
            end
    end

    assign clk2 = temp;

endmodule

LFSR

module lfsr (out, clk, rst);

    output  [4:1] out;
    input clk, rst;

    reg [4:1] w;

always @(posedge clk or posedge rst)

    begin

    if (rst)
        begin
            w = 4'b1011;
        end

    else
        w = {w[3],w[2],w[1]^w[4], w[4]};
    end

assign out=w;

endmodule 

HAMMING

module hamming(din, dout);
    output [6:0] dout;
    input [3:0] din;

    assign dout[6] = din[3];
    assign dout[5] = din[2];
    assign dout[4] = din[1];
    assign dout[3] = din[1] ^ din[2] ^ din[3];
    assign dout[2] = din[0];    
    assign dout[1] = din[0] ^ din[2] ^ din[3];
    assign dout[0] = din[0] ^ din[1] ^ din[3];

endmodule

All this code works properly and computes the correct HAMMING and the clock division works well with the LFSR and works when it is combined as hierarchy design.

When I make the FSM for this code it works upto it computing the hamming number but does not change state when indicated.

• When Switch 1 set: State IDLE
• When Switch 2 set: State 1, Shows 4-bit LFSR number
• When Switch 2 set: State 2, Shows 7-bit Hamming result

The following is my code for the Finite State Machine and following that is the waveform output.

module fsm ( clk , reset , sw1 , sw2 , sw3 , lights );

    input clk, reset, sw1, sw2, sw3;
    output reg [6:0] lights;

    reg[2:0] state;

    wire clkhz;
    wire [3:0] lfsr_out;
    wire [6:0] hout;

    parameter   S0 = 3'b000, S1 =3'b001, S2 = 3'b010; // states

    clock_1hz u1(.clk(clk), 
                    .reset(reset), 
                    .clk2(clkhz));
    lfsr u2(.rst(reset),
                .clk(clkhz),
                .out(lfsr_out));
    hamming u3(.din(lfsr_out),
                    .dout(hout));

always @(posedge clk or posedge reset)
    begin
        if (reset == 1)
            begin
                state <= S0;
            end
        else
            case(state)
                S0: if(sw1 == 1)
                        begin
                            state <= S0;
                        end
                S1: if(sw2 == 1)
                        begin
                            state <= S1;
                        end
                S2: if(sw3 == 1)
                        begin
                            state <= S2;
                        end
                default state <= S0;
    endcase
end

always @(*)
    begin
        case(state)
                S0: lights = 7'b0000000; //led are all off
                S1: lights = lfsr_out; //4bit lfsr shown on led
                S2: lights = hout; // display hamming code result
                default lights = 7'b0000000; //led are all off
        endcase
    end
endmodule

WAVEFORM OF FINITE STATE MACHINE:

I don't think it is a state machine that you need here. From you description of the requirements, perhaps you just need to remember the current switch pressed? If that is the case, you could do something along the lines of:

always @(posedge clk or posedge reset)
  if (reset == 1)
    state <= S0;
  else
    if (sw1)
      state <= S0;
    else if (sw2)
      state <= S1;
    else if (sw3)
      state <= S2;

Now state is remembering the current switch pressed. From your description of the requirements, doing this does not seem to depend on which switch which switch was pressed before that and so it doesn't look like you need a state machine - the behaviour does not depend on the state.

(You don't need all those begins and ends, either. You don't need them if there is only one statement in the branch.)