I am asking about standard Verilog 2001 and not System Verilog extensions. I was sure it was listed as an advantage of tasks, over a function. However, I have this syntax working and it seems to at least simulate well.
{index, value} = sample(val1, val2, operation);
It seems the single bus is not a limitation if it is unpacked to multiple wires? The function needs a similar sample = {fIndex, fValue}; to construct the multiple values. Will synthesis tools have an issue with this?
The return type of a Verilog function must be a single type, and one of those types can be an integral range (a vector). This function can be used in any expression, including the right-hand side of an assignment. The left-hand side of an integral assignment can be a concatenation of multiple integral variables or nets. Consequently, the result of any integral expression, including a function call, can be unpacked into multiple variables or nets.