LANGUAGE SPECIFIC DOUBT, LANGUAGE IS MIPS
I am aware that double precision takes up two registers. ( So If i store in $f5, then I should not mess with $f6)
But it says that odd numbered registers cannot be used for double precision multiplication. (shifted all by one($f5 changed to $f6) and the code worked fine)
Is there a reason for this? Couldnt find much on this anywhere
Anything would be appreciacted, Thanks
The floating point registers are 32-bits wide, so a double (float), which is 64-bits takes 2 registers.
The hardware assumes even/odd pairs to hold all 64-bits of a double, so we always refer to a 64-bit double using the even register number.
Could the hardware use an odd/even pair like $f5,$f6 — hypothetically, of course. For the hardware, to go from an even register number (e.g. $f4) to an odd register number ($f5) we simply change the low bit from 0 to 1 (4=00100; 5=00101). To go from an odd number ($f5) to the next higher even number ($f6) would require a 5 bit addition rather than simply flipping the bit. We would also have to consider whether $f31 pairs with $f0 or what. (Flipping the odd bit (e.g. from $f5) even would get us the same even/odd pair ($f5,$f4 vs. $f4,$f5), so there's absolutely no advantage to that for software, and it would be confusing to have two ways use the same pair.)
But that ($f5,$f6) would require a few extra logic gates, so they don't do that. Offering odd/even pairs would not buy much anyway as software can work with the even/odd restriction just fine, so there's little reason for hardware to offer that. When mixing 32-bit and 64-bit floats software simply chooses even/odd pairs for the 64-bit values — this costs a tiny amount of logic at compile time that is a worthwhile tradeoff. Supporting odd/even would also interfere with the calling convention in parameter passing and preserved registers, so again would be of no particular advantage.
Could the hardware use two arbitrary registers not adjacent — yes, this is also possible, but now we would have to name the two registers, so double floating point instructions would require 6 register names, and no longer fit in 32 bits, and, they would decode quite differently from single precision floating point.
Another alternative is to expand the floating point registers to 64-bits each, eliminating the need for register pairs/pairing entirely. This is done in certain MIPS designs, including MIPS64. It is also back ported to MIPS32 in certain revisions.