I tried to simulate cvfpu
(a floating-point unit written in SystemVerilog) with iverilog, but the compiler gave up every time when there was parameter int unsigned
in source code even if I added -g2005-sv
. Does it mean that int unsigned
is not supported by iverilog? And I'll also be appreciated that you can tell me how to simulate SystemVerilog codes, like cvfpu
, with iverilog (not vcs).
iverilog
does not support all SystemVerilog features.
I tried a trivial example on EDA Playground using the latest version of iverilog
which is available there, and it also generates a syntax error. It uses the -g2012
option to enable SystemVerilog features. The example compiles without errors with other simulators on that site.
If you want to continue to use iverilog
, you can try to contact the developers to see if a newer version is available.
Otherwise, you need to use a different simulator to run simulations with this syntax.