mipscpucpu-architecture

How to find signal values after an instruction is executed in a single-cycle 32-bit MIPS processor?

Consider the following datapath for a single-cycle 32-bit MIPS processor.

Datapath for a single-cycle 32-bit MIPS processor

Suppose the lw instruction is executing in the following program:

lui $t2,0x3f 
ori $t2,$t2,0x11 
lw $t8,4($t2)

Instruction lui is located at address 0x40004044. What are then the signal values for A, B, C, D, and E when the lw instruction is executed? For each signal, answer with either an integer number or write unknown for a signal value where it is not possible to determine an exact value with the given information.

How can I solve this problem? I have been given the answers but I have no idea how to do the actual problem-solving to get to these answers:

The signal values are

A = 24
B = 0x003f0011
C = unknown
D = 0x40004060
E = 0x4000404C

Solution

  • First, since this is a single cycle processor, the fact that there are instructions preceding the lw of interest, affects only the values in registers (including the PC) but not the control signals when the lw executes.

    If the lui instruction is stored at 0x40004044 then the ori at 0x40004048 and the lw at 0x4000404C.  Thus, when the lw is executing, the current PC value is 0x4000404C.

    So, let's start with E, which a PC value: 0x4000404C, the location of the lw instruction.  You can see that this line comes out of the PC register, and goes into the Instruction Memory, which is the fetch for the lw instruction bits.  This PC value also goes to the increment circuit, that adds 4 to the PC value for sequential execution of the next following instruction.

    Next, A is the register number of the target of the lw instruction.  How do we know this?  It is a matter of instruction decoding.  The lw instruction has the I-Type format.  This means that the rs and rt fields are relevant.  It performs R[rt] = M[R[rs]+SignExtImm].  The rs field occupies bits 25:21 and the rt field occupies bits 20:16.  Thus, in lw $t8,4($t2), the $t8 is rt and while from friendly name of $t8 we can know the actual register number value of $24, so 24 base ten (i.e. 2410), by simply looking that up in the Register Name table.

    The B value is the contents of the register whose number is known as source register A1, bits 25:21 aka rs, here $t2.   This value, the contents of register $t2, is understood by following the execution of the prior 2 instructions, which form a 32-bit address into $t2, namely 0x3f0011.

    C is the output of the data memory fetch operation.  It is the value of the memory location 0x3f0015 (from 0x3f0011 + 4 as per the addressing mode).  Since this is an odd address, it will most likely fault rather than producing some value.  If it did not fault, then to determine the value you would have to be given the values stored in the 4 memory locations starting at 0x3f0015.

    D is the computation of the branch target as if the instruction were a branch — however it is not a branch, but non-the-less, the hardware will compute the branch target address only to throw that away.  Hardware works like that in many cases: compute something that we don't necessarily know is relevant, though the computation is done in parallel and just in case, rather than waiting to compute this only when it is truly known whether the value is relevant or not.

    This value is simply (4 << 2), where the 4 comes from the 4 in lw $t8, 4($t2), plus the PC value/location of the lw (plus 4 since the other input is post PC increment of 4).  So, 0x0400404c + 4 + (4<<2) = 0x04004060.