Errors during synthesis

I had written a Verilog code given below for simulation purpose.It is working properly during simulation.

 module read_1(clk,reset);
 input clk,reset;
 reg [0:23]dataout;
 reg htpv;
 reg [0:23]e_data;
 reg[1:24]data_out;
 reg [25:0]cpv,cpv_round,e_av;
 reg [0:23]data[0:0]; 
 parameter threshold =8388608;
 integer i,f1;
 always @(negedge reset) 
  begin
   i=0;
   $readmemb("ppm_data.txt",data); 
   dataout=data[0];
   e_data=24'b0;
  end
always @(negedge clk)
  begin
   f1=$fopen("xxxx.txt","a");
   if(i==0)
   begin
   data_out=dataout[(i*24)+:24];
   e_av=(e_data[0:23])>>4;
   e_data=e_data<<24;
   cpv=data_out+e_av;
   cpv_round=(cpv<threshold)?0:16777215;
   htpv=(cpv_round==0)?1:0;
   e_data[0:23]=cpv-cpv_round;
   $fwrite(f1,"%b",htpv);
   i=i+1;
end
 $fclose(f1);
 end
endmodule

Now I am synthesizing above code using Lattice Diamond, I am getting errors at 'Map Design' step. Errors are given below:-

ERROR - map: Design is empty.
ERROR - map: Errors found in users design.  Output files not written.

Why I am getting these errors and how I can resolve them.

The synthesiser is clever, it removes any logic which cannot influence an output.

You have no outputs, only regs - so all your logic gets optimised away and the design is seen as empty.

Note that $fopen and $fwrite are not synthesisable, so don't count as "outputs"