I'm working on a project and I'm confused with the verilog code that a senior engineer wrote before, he's not in the company right now so I want to know why he write the comparison in this way:
subtractor #(41) sub_sum(expiredSum, {1'b0,dataRead[39:0]}, {1'b0,timeStandard});
assign expiredD = expiredSum[40];//goes high when dataRead>timeStandard
What's the advantage of this? Why didn't he just do
expiredD == (dataRead < timeStandard);
It a more common way in my opinion.
module subtractor( c, a, b );
parameter WIDTH = 1;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] c;
assign c = a - b;
endmodule
I have ran into this kind of issue a few time throughout my career. Even if the original engineer was available, it could be challenging to figure out why something was done a particular several projects latter.
Usually the root cause had to do with the timing and/or area challenges with standard cell library or synthesizer. In your specific case it looks like a 40-bit comparator was less efficient than use forced 41-bit subtractor. This could still be the true.
You should do a trial synthesize and timing analysts. Regardless of the results, add more meaningful comment in the code explaining the rational so it will make sense during code review and whoever will inherit the code latter. Even if the comparator is more efficient this time around. The next technology node or fpga target might be different again. Better to have both with one commented out and good comments explaining it.