system-verilogsystem-verilog-dpi

Exporting task of an instantiated module


I am trying to export several tasks to a C program via DPI-C. The tasks are defined in the module "my_subm" as:

module my_subm;
    task mytask1(...);
    ...
    endtask
    task mytask2(...);
    ...
    endtask
endmodule

And in my main module "main_mod", where "my_subm" is instantiated:

module main_mod;
    my_subm my_subm_i ();
    `include "dpic_exports.svh"

    initial begin
        ...
    end
endmodule

Where "dpic_exports.svh" is:

`ifndef DPIC_EXPORTS
`define DPIC_EXPORTS

export "DPI-C" task my_subm_i.mytask1;
export "DPI-C" task my_subm_i.mytask2;

`endif

When trying to compile it I get an error saying that in "dpic_exports.svh" my_subm_i is an illegal location for a hierarchical name.

What am I doing wrong?

What I need is these tasks to be available from the scope of "main_mod", as the C tasks that will access them are called from that module.


Solution

  • The export statement has to be in the same location as the task/function being exported. Two suggestions: You can create wrapper tasks in your main_mod and export those

    task mytask1;
      my_subm_i.mytask1;
    endtask
    task mytask2;
      my_subm_i.mytask2;
    endtask
    export "DPI-C" task mytask1;
    export "DPI-C" task mytask2;
    

    The other option is to put the export statements inside my_subn_i and use svSetScope(svGetScopeFromName("main_mod.my_subm_i"); in your C code.