system-veriloguvm

Value set by +uvm_set_config_int is not matched

I am trying to set configuration by using this command line option:

+uvm_set_config_int= \*,path_index,1

In a sequence body task, I am looking for the value:

if (!uvm_config_db#(int)::get(null, "", "path_index", i)) begin
end

The value is not found.

If instead of a command line option, I am setting the value in the build phase of the test:

uvm_config_db #(int)::set(null, "*", "path_index", 1)

The value is found by the sequence.

I checked the UVM configuration viewer, and it looks like in both cases scope pattern is the same. Please advise.

Solution

  • Try uvm_bitstream_t instead of int:

    if (!uvm_config_db#(uvm_bitstream_t)::get(null, "", "path_index",i)) begin
end