I have the following scenario : I have a vpi callback that is triggered when an assertion is triggered. In this callback I want to call an export system verilog function I tried to setSvScope before the export but simulator gives me some errors.
Calling an DPI exported routine from a routine that has not been DPI imported is left undefined by the 1800-2012 LRM (See section 35.5.3 Context tasks and functions)
The exported DPI routine when called needs two key pieces of information to behave like any other routine that would have been called by SystemVerilog instead of C. It needs a scope context and a process context.
For the scope, it’s possible to have multiple DPI exports with the same name. In fact, it is possible to have a DPI import/export pair in a module, and that module gets instantiated multiple times. Even though the import calls the same C code, its context gets set from the caller’s scope and that scope gets matched with the exported scope. The DPI provides a svSetScope routine to do this explicitly if the implicit DPI imported routine does not.
For the process, there are many things you can do like disable, or suspend it. The DPI provides no mechanism to set this explicitly.
Some tools(like Questa) do provide a mechanism to do this for a limited set of use cases. For example, you can only call a DPI exported function from non-DPI imported C/C++ code. A task cannot be called because it has the potential to block, and that interferes with any process context.