using xilinx cores in modelsim via .do file

Tool versions:

Modelsim PE 10.4a student edition
Xilinx ISE 14.7

I am trying to use xilinx cores from xilinxcorelib_ver and unisims_ver for simulation but I am seeing this error:

Error: (vsim-3033) ../rtl/verilog/RdidTopLevel.v(72): Instantiation of 'bufg' 
failed. The design unit was not found.

Here is my .do file:

vlib ./work
vmap -modelsim_quiet xilinxcorelib_ver 
        C:/Modeltech_pe_edu_10.4a/xilinxcorelib/xilinxcorelib_ver
vmap -modelsim_quiet unisims_ver 
        C:/Modeltech_pe_edu_10.4a/xilinxcorelib/unisims_ver
set top_level spi_rdid_tb
vsim -novopt $top_level
vsim -lib unisims_ver

I am instantiating the bufg like so:

BUFG bufg(.I(clkNoBuf), .O(clk));

What exactly am I doing wrong? I want to be able to map my source directory that compxlib created and include this in my designs so that I can simulate from anywhere with a simple .do file. I've looked around for the past few hours and can't seem to find anything that works.

EDIT: When I run this, the GUI in modelsim has these libraries mapped with all the compiled sources, but my designs still can't see them.

Solution

I figured out my mistake, reference the template after the explanation. For anyone wondering how to get compxlib to work with an automated script from step 1:

Ensure the path to your core bin directory where compxlib.exe lives (NOTE: this is for Xilinx, but Altera/Intel might be similar)

C:\Xilinx\*Tool\*version\ISE_DS\ISE\bin

Once your system has reference to your bin directory, run the following from a terminal/command line. This will compile the cores for your edition of ModelSim, all architectures, and languages to your desired directory:

>>> compxlib -s mti_pe -arch all -l all -w -lib all -dir 
    c:/Modeltech_pe_edu_10.4a /xilinxcorelib

from the .do/.tcl script, perform the following:

# 0) Create work directory for modelsim
vlib ./work

# 1) map core libs
vmap -modelsim_quiet xilinxcorelib_ver 
    C:/Modeltech_pe_edu_10.4a/xilinxcorelib/xilinxcorelib_ver
vmap -modelsim_quiet unisims_ver 
    C:/Modeltech_pe_edu_10.4a/xilinxcorelib/unisims_ver

# 2) Compile files in use order
# vcom -93 -work work dirToSrc/file.vhd
# vlog ../rtl/verilog/*.v

# 3) use specific top level
set top_level spi_rdid_tb
# vsim -novopt $top_level # use this line instead of next if no core lib
vsim -novopt -L unisims_ver work.$top_level

# 4) the rest of your tb stuff for automation