verilogsystem-verilogsystem-verilog-assertions

How to sample covergroup at the occurence of a certain sequence?


module testbench;
  
  bit [2:0] A;
  bit [2:0] data[];
  int i;
  bit [2:0] b;
  
  covergroup cov_grp;
    c1 : coverpoint A {
      bins b1 = {0,1,2};
      bins b2 = {3,4,5};
      bins b3 = {6,7};}
  endgroup
  
  sequence seq;
    (b == 'd7);
  endsequence
  
  initial 
    begin
      cov_grp cov_ins = new();
      data = new[10];
      for(i=0;i<8;i++)
        begin
          
          data[i] = $random;
          A = data[i];
          assert property @(seq) cov_ins.sample();
        end
    end
  
endmodule

I want to sample for the covergroup instance cov_ins when sequence seq occurs. When b = 'd7 it should sample ...............................................................................................................................................................................................................................................................................................................


Solution

  • Just as your covergroup needs an event to trigger sampling, a sequence needs an event to know when to sample and evaluate the expression b = 'd7 (BTW, your testbench never sets b).

    And it's not clear from your testcase why you even need to be using a sequence that is a simple Boolean expression. You could just write:

    if (b == 'd7) cov_ins.sample();
    

    But assuming your sequence is more complex, then you need a clock in your sequence and need to write something like

    sequence seq;
      @(posedge clk) (b == 'd7)[->1]; // when b transitions to 'b7
    endsequence
    
    covergroup cov_grp @seq; // instead of calling sample()
        c1 : coverpoint A {
          bins b1 = {0,1,2};
          bins b2 = {3,4,5};
          bins b3 = {6,7};}
      endgroup