system-veriloguvm

set_inst_override_by_type() override fail

I'm trying to get a object value from before/after override by factory. Basically I implement 2 objects and they have constrainted i_type.

class cfg extends uvm_object;
  rand int unsigned i_type;
 
  `uvm_object_utils_begin(cfg);
  `uvm_field_int (i_type, UVM_ALL_ON)
  `uvm_object_utils_end
 
    constraint i_tpye_c { i_type == 'h88; }
  function new(string name="cfg");
    super.new(name);
  endfunction : new
endclass
 
class c_0 extends cfg;
  `uvm_object_utils(c_0)
  constraint i_type_c { i_type == 2'b11; }
  function new(string name="cfg_0");
    super.new(name);
  endfunction : new
endclass

There are 2 problems.

  1. When I check the i_type value before and after override, they are all 00. Actually I though that before override I can get a i_type =88 and after override i_type = 2'b11. How do I correctly get the i_type value?

For your understand I implemented in https://edaplayground.com/x/LpE2

Solution

  • You declared the i_type variable as an int type. When you constructed the object containing the variable using create, it set i_type to 0, which is the default value of int types.

    Since you did nothing else to change the value of the variable, it prints out as 0.

    You added constraints for the variable, but they only have effect when you call randomize on the object. Therefore, you need to call randomize, for example:

    m_cfg.randomize();