system-veriloguvm

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

Here here different UVM class signatures:

virtual class uvm_env extends uvm_component;
virtual class uvm_scoreboard extends uvm_component;
virtual class uvm_monitor extends uvm_component;

class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) 
                    extends uvm_sequencer_param_base #(REQ, RSP);

class uvm_driver #(type REQ=uvm_sequence_item,
                   type RSP=REQ) extends uvm_component;

virtual class uvm_sequence #(type REQ = uvm_sequence_item,
                             type RSP = REQ) extends uvm_sequence_base;

In above we can see uvm_sequencer, uvm_driver and uvm_sequence are parametrized classes. Why uvm_sequence class is still abstract one, while other two are not?

Solution

  • The uvm_sequencer class is not defined as virtual because it is already useful as it is without being extended.

    The uvm_dirver class is not defined as virtual probably because of legacy from OVM. There were a couple of rare cases it could be used without extension.