Is it possible to tie ports high always high outside of top module?

I'm programming the Xilinx BASYS 3, Artix 7 board. It has 7-seg display with 4 anode ports. When I ignore them in code they are low causing the 7-seg to be on. Is there a way to make tie them high in the constrain.xdg file for example? It is not ideal to always has anode outputs even when I'm programming the VGA.

module top(
  input wire clk,
  ...
  output wire [3:0] an
);
  ...
  assign an = 4'b1111; // <- I want this done automatically outside of my VGA program / top module
  ...
endmodule

The Xilinx FPGA IOB has an option of adding a weak pullup resistor, using a property in the constraints file. Four of these should turn the display segments off.

Here is a link to the description of how the pullup works.
PULLUP

• The basic description looks like this:
  

• The constraints file syntax is given a little further down the page:
  

Here is the board schematic with the display interface pins in green.

Putting it together as properties:

set_property PULLUP TRUE [get_ports an[0]]
set_property PULLUP TRUE [get_ports an[1]]
set_property PULLUP TRUE [get_ports an[2]]
set_property PULLUP TRUE [get_ports an[3]]

I recommend adding these to the bottom of your constraints file and building. Take a look at the log file when the build is done, and how the tool responded when the new properties were added.

You might need to use the pulltype property instead; its very similar syntax is is documented on the same page as pullup.