I have created a model of a design in SystemVerilog. It uses fixed point maths. Some top level parameters of the module are used to specify what scaling factor to use for the calculation within the module. This affects the values of predefined constants and also how the scale down operation and rounding is performed.
Right now I have multiple predefined constants and then choose one of them based on the parameter value using if..else.. block. There are multiple different functions that are almost identical except what constants they use during calculation and how the result is scaled down.
My question is, is it possible to pass the top level testbench module parameter into the package and use that to choose what value the constants should have i.e parameterize the package using testbench top level module parameter?
I am from VHDL background and the `if vs #if confuses me. Also, I am not sure if what I am trying to do is possible in SystemVerilog using testbench module top level parameters.
Your question is very close to an XY problem. SystemVerilog packages cannot be parameterized, nor can you select a different package to import based on a parameter. There are many possible approaches if we had more specific details about what you ultimately need to accomplish.
If you are going to have different top-level testbenches, you can have each testbench import different packages and the different parameter values down to your design.
You can compile different versions of your package into different libraries, and chose the library you want at the same time you choose the testbench you want. Compilation scripts will be a tools specific issue, not part of the SystemVerilog language.
You can put functions in your package that select return values based on the top-level testbench parameters.