Design is a serial adder. It takes 8-bit inputs A and B and adds them in a serial fashion when the goinput is set to 1. The result of the operation is stored in a 9-bit sum register, The block diagram is attached. I am using Quartus II 13.0sp1 (64-bit) Web Edition.
Errors: Error (10170): Verilog HDL syntax error at LAB9b.v(56) near text "â"; expecting ":", or "," i have not written this text "â" anywhere in the code but still it is sowing me syntax error near "â" .??
Following is the Code written :-
module LAB9b(A, B, start, resetn, clock, sum);
input [7:0] A, B;
input resetn, start, clock;
output [8:0] LEDR;
// Registers
wire [7:0] A_reg,B_reg;
wire [8:0] sum;
reg [1:0] temp;
reg cin;
// Wires
wire reset, enable, load;
wire bit_sum, bit_carry;
// Confrol FSM
FSM my_control(start, clock, resetn, reset, enable, load);
// Datapath
shift_reg reg_A( clock, 1’b0, A, 1’b0, enable, load, A_reg);
shift_reg reg_B( clock, 1’b0, B, 1’b0, enable, load, B_reg);
// a full adder
assign temp [1:0] = A_reg[0] + B_reg[0] + cin;
assign bit_sum = temp [0];
assign bit_carry = temp [1];
always @(posedge clock)
begin
if (enable)
begin
if (reset)
cin <= 1’b0;
end
else
cin <= bit_carry;
end
shift_reg reg_sum( clock, reset, 9’d0, bit_sum, enable, 1’b0, sum);
defparam reg_sum.n = 9;
endmodule
module FSM(start, clock, resetn, reset, enable, load);
parameter WAIT_STATE = 2’b00, WORK_STATE = 2’b01, END_STATE = 2’b11;
input start, clock, resetn;
output reset, enable, load;
reg [1:0] current_state, next_state;
reg [3:0] counter;
// next state logic
always@(*)
begin
case(current_state)
WAIT_STATE:
if (start) next_state <= WORK_STATE;
else next_state <= WAIT_STATE;
WORK_STATE:
if (counter == 4’d8) next_state <= END_STATE;
else next_state <= WORK_STATE;
END_STATE:
if (»start) next_state <= WAIT_STATE;
else next_state <= END_STATE;
default: next_state <= 2’bxx;
endcase
end
// state registers and a counter
always@(posedge clock or negedge resetn)
begin
if (»resetn)
begin
current_state <= WAIT_STATE;
counter = ’d0;
end
else
begin
current_state <= next_state;
if (current_state == WAIT_STATE)
counter <= ’d0;
else if (current_state == WORK_STATE)
counter <= counter + 1’b1;
end
end
// Outputs
assign reset = (current_state == WAIT_STATE) & start;
assign load = (current_state == WAIT_STATE) & start;
assign enable = load | (current_state == WORK_STATE);
endmodule
//
//
module shift_reg( clock, reset, data, bit_in, enable, load, q);
parameter n = 8;
input clock, reset, bit_in, enable, load;
input [n-1:0] data;
output reg [n-1:0] q;
always@(posedge clock)
begin
if (enable)
if (reset)
q <= ’d0;
else
begin
if (load)
q <= data;
else
begin
q[n-2:0] <= q[n-1:1];
q[n-1] <= bit_in;
end
end
end
endmodule
’ is not ' (notice the shape difference). Verilog works with the apostrophe character (', ASCII 0x27). Your ’ is likely an extended ASCII character. There is also a » character, which I believe should be !.
I'm guessing you wrote your code in word editor (ex Microsoft Word, LibreOffice Writer, Apple iWork, etc). These kinds of editors tend to swap ' for ’ while you type because it is more visually appealing for humans. Email clients and some messaging apps tend to do this too.
You should always write your code in a plain texted editor or an editor intended for writing code. Emacs and Vim are popular editors for writing code; syntax highlighting plugins are available for both. An IDE, like Eclipse, is another option. Notepad does work as well.
I also noticed you used an assign statement on the reg type temp. This is not legal in Verilog because assign statements can only be done on net types (e.g. wire). You may have other compiling errors that will show up after fixing ’ and », the error message will likely be more helpful.
The compiler will not flag it, but the recommended coding style is to use blocking assignments (=) inside combination block (always@(*)), not non-blocking (<=).