Below is my 1-bit ALU which is proven to work. Now I would like to use this 1-bit ALU in an 8-bit ALU, and it needs to pass a testbench. So far I compiled an 8-bit ALU code, but it doesn't seem to work.
module ALUSlice(A,B,CI,M,S,F,CO); //Code for 1-bit
input A,B,CI,M,S;
output F,CO;
wire [3:0] TF;
wire [3:0] TC;
FullAdder F1(TF[3],TC[3],A,B,CI);
assign TF[0] = A & B;
assign TF[1] = A | B;
assign TF[2] = ~A;
assign TC[2:0] = 0;
Dual4to1Mux Mux1(F,CO,{M,S},TF,TC);
endmodule
module ALU8Bit(S1,S0, A, B, CarryIn, CarryOut, F);//What I have so far
input [7:0] A,B;
input S1,S0,CarryIn;
output [7:0] F;
output CarryOut;
wire [7:0] C;
ALUSlice A0(F[0],C[0],A[0],B[0],CarryIn,S0,S1);
ALUSlice A1(F[1],C[1],A[1],B[1],C[0],S0,S1);
ALUSlice A2(F[2],C[2],A[2],B[2],C[1],S0,S1);
ALUSlice A3(F[3],C[3],A[3],B[3],C[2],S0,S1);
ALUSlice A4(F[4],C[4],A[4],B[4],C[3],S0,S1);
ALUSlice A5(F[5],C[5],A[5],B[5],C[4],S0,S1);
ALUSlice A6(F[6],C[6],A[6],B[6],C[5],S0,S1);
ALUSlice A7(F[7],CarryOut,A[7],B[7],C[6],S0,S1);
endmodule
Without a more complete picture of everything, its not easy to tell if this is your only issue. But one reason this might be failing is it seems you did not hook up your ALUSlice modules correctly in your ALUBit. The port (io) order of the ALUSlice module should be inputs followed by outputs, but you have outputs followed by inputs in your instantiations. The best way to void these kinds of bugs is to explicitly connect ports to their respective lines rather than relying on order, like so:
ALUSlice A0(.A(A[0]), .B(B[0]), .CI(CarryIn), .M(S1), .S(S0), .F(F[0]), .CO(C[0]));
This way, everything is connected exactly as you intend (ie, A[0] is connected to the A input, B[0] to B, CarryIn to CI, etc) without making mistakes with the order, or when you add new ports or take any away, everything is still hooked up as expected.