shift register using dff verilog

I want to create a shift register using d-flip-flop as basic structural element. code:

dff:

  module dff(d,q,clk,rst);

  input d,clk,rst;
  output reg q;

  always @(posedge clk)
     begin:dff_block
        if(rst==1'b1)
          q=1'b0;
        else
          q=d;
     end
  endmodule

shift register:

  module shift_register(s1,d,clk,s0,q);
  parameter n=3;

  input  s1,clk;
  input [n:0] d;

  output s0;
  output [n:0] q;

  genvar i;

  assign d[3]=s1;


  generate
  for(i=0; i<=n; i=i+1)
     dff U1(.d(d[i]),.q(q[i]),.clk(clk));
  endgenerate

  assign q[3]=d[2];
  assign q[2]=d[1];
  assign q[1]=d[0];
  assign q[0]=s0;



  endmodule

test bench:

  module tb();

  parameter n=3;
  reg [n:0] d;
  reg s1,clk;

  wire [n:0] q;
  wire s0;


  shift_register UUT(.s1(s1),.d(d),.clk(clk),.q(q),.s0(s0));

  initial begin

  d=4'b0000;
  clk=0;
  end


always
begin:clok
#10 clk=~clk; s1=1;

end
endmodule

I think test bench has the problem.I have tried to give s1 values for every #10 while clk=1 but again does not work.

This code does not give me waveforms for q and s0.I cant find whats wrong.Any ideas?

Solution

you have several problems with the code.

q is an output reg of dff; q[i] is passed as q to dff. q[i] gets also assigned in within the assign statement. So, you have multiply driven wire q[i] which most likely gets resolved to x and never changes. You have your i/o swapped around somewhere.
you do not assign anything to s0, so it does not change and does not produce any waveform.
in this particular case blocking assignments within the flop will not pay any role, but in general they could cause unpredictable simulation results. Use non-blocking.
there is not much sense in the generate loop there. You can pass full vectors tot he dff and can flop full vectors as well.
It looks like you get confused int teh direction of the assign statement. It implies direction. assign q[0] = s0; means assign value of s0 to the wire q[0], not vice versa.