[SOLVED] How to fix Error (10170): Verilog HDL syntax error at <filename> near text "("; expecting ";"

How to fix Error (10170): Verilog HDL syntax error at <filename> near text "("; expecting ";"

I am trying to instantiate a NiosII core in Quartus II and get the following compilation error message:

Error (10170): Verilog HDL syntax error at myNiosII_inst.v(1) near text "(";  expecting ";"

I added myNiosII.qip and myNiosII_inst.v files to my Quartus II project from Qsys.

The error relates to file myNiosII_inst.v:

myNiosII u0 (
    .clk_clk         (<connected-to-clk_clk>),         //      clk.clk
    .reset_reset_n   (<connected-to-reset_reset_n>),   //    reset.reset_n
    .switches_export (<connected-to-switches_export>), // switches.export
    .leds_export     (<connected-to-leds_export>)      //     leds.export
);

Which is instantiated in my top level file DE2_115_top.v as follows:

myNiosII u0 (
    .clk_clk         (CLOCK_50),         //      clk.clk
    .reset_reset_n   (KEY[0]),   //    reset.reset_n
    .switches_export (SW), // switches.export
    .leds_export     ({LEDR,LEDG})      //     leds.export
);

Solution

myNiosII_inst.v is an instantiation template - an example of how you should use myNiosII - not a source file in its own right. You should remove it from the list of project source files.