Verilog If statement -Appears to be triggering before Condition

Why does r_D <= 8'h40 execute before w_Rx_DV == 1'b1 according to below code and waveform? R_D should not be assigned any value until w_Rx_DV goes high.

Thank you for any comments

Joe

  module main(

  input           i_Clock,
  input           i_Rx_Serial, 
  output          o_PWM
                   );

  reg              r_Load ;         
  reg [7:0]        r_D =0;
  wire             w_Rx_DV;
  wire [7:0]       w_RX_Byte;
  reg [7:0]        r_RX_Byte;        


  PWM PWM(
     .i_Clock(i_Clock),
     .i_Load(r_Load),   
     .i_D (r_D),         
     .o_PWM(o_PWM)   

  );

  rx rx(
     .i_Clock (i_Clock),
     .i_Rx_Serial (i_Rx_Serial),
     .o_Rx_DV (w_Rx_DV),
     .o_Rx_Byte (w_RX_Byte)
   );


always @ (posedge i_Clock)
  begin
    r_Load <= 0;
    if(w_Rx_DV == 1'b1) ;
      begin
        r_RX_Byte <= w_RX_Byte;
          if(r_RX_Byte ==8'h0)
            begin
                r_D <= 0;
                r_Load <= 1;
            end
          if(r_RX_Byte == 8'h3F)        
            begin
                 r_D <= 8'h40;
                 r_Load <= 1;
            end
     else
        begin
        r_Load <= 0;
        end
     end
     end


endmodule

waveform

Why does r_D <= 8'h40 execute before w_Rx_DV == 1'b1

Because you have a semicolon after the if here:

if(w_Rx_DV == 1'b1) ;
                 // ^ End of if statement.