CMA Allocation Fault on Petalinux 2020.2 (Zynq-7000)
I want to use 1920x1080 (or more) on my custom Zynq-7000 Board. Mode 1024x768 works nice.
There is CMA allocation error, when I try to use FullHD. I added some output to source code (output below is for 2560x1600, it is the same for 1920x1080, excepting buffer size):
[12:09:34:466] xlnx-pl-disp amba_pl:xlnx_pl_disp: surface width(2560), height(1600) and bpp(24)
[12:09:34:474] xlnx-pl-disp amba_pl:xlnx_pl_disp: bytes per line after alignment: 12288000
[12:09:34:480] xlnx-pl-disp amba_pl:xlnx_pl_disp: allocating 12288000 bytes with kzalloc()...
[12:09:34:488] xlnx-pl-disp amba_pl:xlnx_pl_disp: OK
[12:09:34:491] xlnx-pl-disp amba_pl:xlnx_pl_disp: init gem object...
[12:09:34:497] xlnx-pl-disp amba_pl:xlnx_pl_disp: OK
[12:09:34:500] xlnx-pl-disp amba_pl:xlnx_pl_disp: creating mmap offset...
[12:09:34:505] xlnx-pl-disp amba_pl:xlnx_pl_disp: OK
[12:09:34:508] xlnx-pl-disp amba_pl:xlnx_pl_disp: gem cma created with size 12288000
[12:09:34:514] xlnx-pl-disp amba_pl:xlnx_pl_disp: failed to allocate buffer with size 12288000
[12:09:34:522] xlnx-pl-disp amba_pl:xlnx_pl_disp: Failed to create cma gem object (12288000 bytes)
[12:09:34:527] xlnx-pl-disp amba_pl:xlnx_pl_disp: drm_fb_helper_single_fb_probe() returns -12
[12:09:34:536] xlnx-pl-disp amba_pl:xlnx_pl_disp: Failed to set initial hw configuration.
[12:09:34:541] xlnx-pl-disp amba_pl:xlnx_pl_disp: failed to initialize drm fb
As I see, the issue goes from this line (drm_gem_cma_helper.c)
cma_obj->vaddr = dma_alloc_wc(drm->dev, size, &cma_obj->paddr,GFP_KERNEL | __GFP_NOWARN);
I try to change some settings:
- increase CMA Size in Kernel config (it was 128, now 256 Mb)
- increase CMA Areas number in Kernel config (from 7 to 20)
- add reserved memory to Device Tree
- add coherent_pool option to bootargs
I get the same fault anyway.
Please help to find the reason and solve my issue.
Many thanks!
With regards, Maksim
Solution
The only solution I've found is to change kernel base address from 0x18000000 to 0x11000000 (as shown on screenshot).
Unfortunately, I don't have complete explanation on how it helps.
With regards, Maksim
- Armv7 MMU on the ZYNQ-7000 not starting the virtualization
- Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
- Where to force xilinx ISE to use block-rams?
- Is CRC Calculation Faster on Xilinx Alveo U280 FPGA Using a Custom Algorithm or a Lookup Table?
- How to implement pipelined floating point accumulation in II=1 in Vitis/Vivado HLS?
- Timing simulation in Vivado giving an error
- Is it possible to tie ports high always high outside of top module?
- How to fix [Common 17-1293] error in Xilinx Vivado?
- How to initialize contents of inferred Block RAM (BRAM) in Verilog
- Implementing hardware that divides an 8 bit number by 3 (11) in binary
- Can SYSCLK be included in FPGA Xilinx vivado testbenches?
- Isim not running
- how to add python in xilinx vitis
- Timing closure problems in FIFO
- Xilinx Vivado schematic for if else statements
- difference between Xilinx solarflare scaleout onlod, solarflare onload, and solarflare TCPDirect?
- Inferring a True Dual Port RAM (Xilinx and Intel compatible) in Verilog
- 'case item is unreachable' in Vivado synthesis process
- Why does the Inferred Latch error occur during the synthesis process?
- What is the granularity of the AXI-ACE protocol?
- Restricting Verilog parameters
- Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array
- Vitis PetaLinux build cant fetch required files while building an application project
- Address of a struct used to set MSI Base address, how does it work? (in Xilinx PCIe RC driver)
- How To Convert .bit file to .bin
- of_node_name_eq for device tree node label
- using xilinx cores in modelsim via .do file
- Add hwspinlock Linux Driver to Petalinux project
- How to use XADC's GPIO on Xilinx KC705 FPGA
- Need help in converting verilog module without input & output ports into synthesizable. Because module without input/output ports is not synthesizable