Verilog Coding Not Performing as Expected

new using Verilog and coding the Upduino v3.1. Set a PLL module, using its output clock to increment a counter until it reaches 2000, and toggle the output LED. This is code:

module main_pll(REFERENCECLK, PLLOUTCORE, LED);

input REFERENCECLK;  
output PLLOUTCORE;
output wire LED;

wire pllout;
reg [15:0] counter;
reg temp;

pllG pllmpd(.ref_clk_i(REFERENCECLK), .rst_n_i(), .outcore_o(PLLOUTCORE),.outglobal_o());

assign pllout = PLLOUTCORE;
assign LED = temp;
initial temp <= 1'b0;
initial counter <= 16`b0;

always @(posedge pllout) begin
    counter <= counter + 1;
    if (counter == 2000) begin
        counter <= 0;
        temp <= ~temp;
    end
end

endmodule

The output LED doesn't toggle and not clear what the issue could be.

Can you please help me understanding what I am doing wrong?

Thanks, Gus

ice40 sets all registers to zero and IIRC unconnected port to GND (1'b0). Thus, the PLL will not start if nothing is passed to rst_n_i. The following code was tested on an ice40UP5K-B-EVN:

module main(    
    input   wire    REFERENCECLK,//12 MHz clock on pin 35 (GPLL_IN/PCLKT0_1)
    output  wire    PLLOUTCORE, // pin 28
    output  reg     LED // will blink with ~3 Hz, mapped to pin 40 (RGB1=green LED)
    );

reg [21:0] counter;// ice40 set everything to zero as default

always @(posedge PLLOUTCORE)
begin
    counter <= counter + 1;
    LED     <= counter ? LED : ~LED;
end
    
testpll pllmpd(
    .ref_clk_i(REFERENCECLK),
    .rst_n_i(1'b1), //this is important, else the nrst will be held at 0
    .outcore_o(PLLOUTCORE), // 24 MHz out
    .outglobal_o()
    );

endmodule