Is it possible for always block to be executed more than once in a time step? That is, execute immediately every time the signal in the sensitive list changes?If not, are there rules about how to behave in this situation?
In general, Verilog implements event-driven simulation and will continue running the same time step evaluation till there are active events. As a result, a generic always can be re-evaluated multiple times in a single step.
For example, if there are several signals on the sensitivity list and they change in some order during a single step evaluation, the always block can be re-evaluated several times. Compilers usually do optimizations to avoid multiple re-calculations.
So, in the following it is possible that the first block would be executed twice: when b changes and then when a changes. If compiler is clever enough, it will always update 'a' first and then go to evaluate the always block, saving one calculation.
always @(a,b)
...
always @* a = b | c;
another possibility if you have something like a loop situation. Here 'a' changes inside the block, causing its re-evaluation. This could be a source of infinite simulation loop.
always @(a,b)
a = b | c;
There are multiple other situations. But the rule of thumb is that in general you should no worry about it. The result of such simulation should be correct in any case due to the event-driven nature of Verilog.
What you have to do is to figure out how to correctly use blocking/non-blocking assignments and edged sensitivity lists to avoid races and infinite loops.