SystemVerilog array of interfaces with unique parameters

I have a module (lets call it "mem") that has array of interfaces as a port, parameter NB_ITFS that declares the number of interfaces and a data WIDTH parameter.

module mem
    #(NB_ITFS=2)
    (itf itfa [NB_ITFS-1:0]);
    logic [31:0] data [NB_ITFS-1:0];
    always_comb
    begin
        data[0] = {4{itfa[0].data}};
        data[1] = {2{itfa[1].data}};
        data[2] = itfa[2].data;
    end
endmodule

Interface looks like this:

interface itf #(WIDTH = 8)();
    logic [WIDTH-1:0] data;
endinterface

How can I create an array of interfaces where every interface has unique parameters? How can I pass them to "mem" module?

Example:

module MyModule #(NB_ITFS=2) ();
    for (genvar i = 0; i<NB_ITFS; i++) begin : ITFA_GEN
        case (i)
            0: itf #(8) itf_if();
            1: itf #(16) itf_if();
            default: itf #(32) itf_if();
        endcase
    end

    mem #(.NB_ITFS(NB_ITFS)) my_mem (.itfa(itf_if));
endmodule

I've tried to connect everything like in example, but it doesn't compile or synthesize.

// Code your testbench here
// or browse Examples
interface itf #(WIDTH = 8)();
    logic [WIDTH-1:0] data;
endinterface

module mem
    #(NB_ITFS=2)
    (itf itfa [NB_ITFS-1:0]);
    logic [31:0] data [NB_ITFS-1:0];
    always_comb
    begin
        data[0] = {4{itfa[0].data}};
        data[1] = {2{itfa[1].data}};
        data[2] = itfa[2].data;
    end
endmodule

module MyModule #(NB_ITFS=3) ();
    itf itf_p [NB_ITFS-1:0](); 
    defparam itf_p[0].WIDTH=8;
    defparam itf_p[1].WIDTH=16; 
    defparam itf_p[2].WIDTH=32;
      
     
   mem #(.NB_ITFS(NB_ITFS)) my_mem (.itfa(itf_p));
endmodule

Above code fix your issue. I tried on all simulator on edaplayground. it is only not supported for VCS.