Verilog state machine state/next_state style

I'm a Verilog beginner, and I'm trying to learn about the best ways to implement FSMs on the common FPGA platforms.

I have seen a number of papers (e.g., this one) that encourage a state/next_state style like this:

always @(posedge clock)
  state <= next_state;

always @(posedge clock)
  [...some logic that sets next_state...]

I find this confusing because it's going to insert an extra and unnecessary clock cycle. For example, if the second always block updates next_state at clock N, then at clock N+1, state will initially still have its old value and won't be guaranteed to have updated to next_state until clock N+2. (Please correct me if that's wrong.)

Why is this style considered best practice given that is causes the insertion of an extra clock cycle on every state change?

Please correct me if that's wrong.

The paper you linked to does not recommend what your question states.

The paper does recommend 2 always blocks:

1. One sequential block to set the current state
2. One combinational block to set the next state

For example, refer to section 5. Two Always Block FSM Style (Good Style).

always @(posedge clock)
  state <= next_state;

always @(state or ...)
  [...some logic that sets next_state...]

For the combinational block, see also the recommended practice in section 12.2 @* Combinational sensitivity list.