I’m somewhat new to Verilog, and have inherited a project created by someone else. It uses a module instantiation technique for which I don't understand the intent. Basically two different module types are created. In one of the module instantiations, the name of the other type is used as the instance name. I will provide a simplified code example:
module bidirectional_filter #(
parameter SIZE = 4,
parameter MAX = 5'd10 //min 2, max 32!
)(
input wire clk,
input wire res,
input wire sync, // sync period
input wire [(SIZE-1):0]in,
output reg [(SIZE-1):0]out
);
// do bidirectional filter stuff
endmodule
module unidirectional_filter #(
parameter SIZE = 4,
parameter MAX = 5'd10 //min 2, max 32!
)(
input wire clk,
input wire res,
input wire sync, // sync period
input wire [(SIZE-1):0]in,
output reg [(SIZE-1):0]out
);
// do unidirectional filter stuff
endmodule
module m_top #(
parameter IN_FREQ_HZ = 25000000
)(
// IO list
);
// do stuff
bidirectional_filter #(
.SIZE( 17 ),
.MAX( 2000 / 100 )
) unidirectional_filter (
.clk( clk ),
.res( res ),
.sync( test_error_sync ),
.in( xcheck_filter_in[17 -1:0] ),
.out( xcheck_error_filtered[17 -1:0] )
);
// do stuff
endmodule
Will it instantiate a bidirectional_filter or unidirectional_filter module? My intuition says that it will just instantiate a bidirectional_filter that is named "unidirectional_filter".
Module definition names and instance names exist in two different name spaces. There is no conflict when reusing the same identifiers (see section 3.13 in the IEEE 1800 SystemVerilog LEM).
Although it is allowed, I would say it is a very bad practice to use the same name of a module as an instance name.
Without seeing more code, I can only guess why they might’ve wanted to do this. Perhaps their scripts relied on seeing the unidirectional_filter instance name regardless of which module was being used.