[SOLVED] Systemverilog/Verilog VCP2000 “Syntax error. Unexpected token: class[

Systemverilog/Verilog VCP2000 “Syntax error. Unexpected token: class[_IDENTIFIER].”

I could not figure out what is wrong with the code here :

https://www.edaplayground.com/x/SpPU

Code snippet

1 // Code your testbench here
2 // or browse Examples
3
4 class myclass;
5 endclass

Error message

[2024-09-02 08:46:01 UTC] vlib work && vlog '-timescale' '1ns/1ns' '-v95' +incdir+$RIVIERA_HOME/vlib/uvm-1.1d/src -l uvm -err VCP2947 W9 -err VCP2974 W9 -err VCP3003 W9 -err VCP5417 W9 -err VCP6120 W9 -err VCP7862 W9 -err VCP2129 W9 design.sv testbench.sv  && vsim -c -do "vsim +access+r; run -all; exit"  
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library "work" attached.
work = /home/runner/work/work.lib
ERROR VCP2000 "Syntax error. Unexpected token: class[_IDENTIFIER]." "testbench.sv" 4  6
WARNING VCP2515 "Undefined module: gen_pkt was used. Port connection rules will not be checked at such instantiations." "testbench.sv" 36  15
FAILURE "Compile failure 1 Errors 1 Warnings  Analysis time: 0[s]."
Exit code expected: 0, received: 255
Done

The settings of the simulator are indicated at the 1st line of the error message. I’ve googled this topic but most of the issues were just due to lack of ;

Solution

The -v95 flag forces the simulator to compile code as Verilog IEEE1364-1995 which doesn't support class. By removing the flag, the simulator can compile the code as SystemVerilog. SystemVerilog supports class, typedef, enum, int, and other keywords used in your code from the edaplaygroud link.